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Searched refs:BFM (Results 1 – 14 of 14) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/r600/sb/
Dsb_bc_fmt_def.inc483 BC_FIELD(TEX_WORD0, BC_FRAC_MODE, BFM, 5, 5)
494 BC_FIELD(TEX_WORD0, BC_FRAC_MODE, BFM, 5, 5)
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.h420 BFM, // Insert a range of bits into a 32-bit word. enumerator
DAMDGPUInstrInfo.td284 def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>;
DSIInstructions.td1957 multiclass BFMPatterns <ValueType vt, InstSI BFM, InstSI MOV> {
1960 (BFM $a, $b)
1965 (BFM $a, (MOV (i32 0)))
DSIISelLowering.cpp4868 SDValue BFM = DAG.getNode(ISD::SHL, SL, IntVT, in lowerINSERT_VECTOR_ELT() local
4872 SDValue LHS = DAG.getNode(ISD::AND, SL, IntVT, BFM, ExtVal); in lowerINSERT_VECTOR_ELT()
4874 DAG.getNOT(SL, BFM, IntVT), BCVec); in lowerINSERT_VECTOR_ELT()
DAMDGPUISelLowering.cpp4285 NODE_NAME_CASE(BFM) in getTargetNodeName()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SchedCyclone.td170 // ASRV,LSLV,LSRV,RORV,BFM,SBFM,UBFM
DAArch64SchedThunderX2T99.td553 def : InstRW<[THX2T99Write_1Cyc_I012], (instregex "^BFM")>;
554 def : InstRW<[THX2T99Write_1Cyc_I012], (instregex "(S|U)?BFM.*")>;
DAArch64SchedA57.td160 def : InstRW<[A57Write_2cyc_1M], (instregex "BFM")>;
DAArch64InstructionSelector.cpp2861 MachineInstr &BFM = in selectMergeValues() local
2870 constrainSelectedInstRegOperands(BFM, TII, TRI, RBI); in selectMergeValues()
DAArch64ISelDAGToDAG.cpp1917 SDNode *BFM = CurDAG->getMachineNode(Opc, dl, MVT::i64, Ops64); in tryBitfieldExtractOp() local
1920 MVT::i32, SDValue(BFM, 0), SubReg)); in tryBitfieldExtractOp()
DAArch64SchedFalkorDetails.td1205 def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^(S|U)?BFM(W|X)ri$")>;
DAArch64SchedKryoDetails.td447 (instregex "(S|U)?BFM.*")>;
DAArch64InstrInfo.td1687 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;