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Searched refs:BaseOpc (Results 1 – 6 of 6) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrArithmetic.td924 multiclass ArithBinOp_RF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
933 def NAME#8rr : BinOpRR_RF<BaseOpc, mnemonic, Xi8 , opnodeflag>;
934 def NAME#16rr : BinOpRR_RF<BaseOpc, mnemonic, Xi16, opnodeflag>;
935 def NAME#32rr : BinOpRR_RF<BaseOpc, mnemonic, Xi32, opnodeflag>;
936 def NAME#64rr : BinOpRR_RF<BaseOpc, mnemonic, Xi64, opnodeflag>;
966 def NAME#8mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi8 , opnode>;
967 def NAME#16mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi16, opnode>;
968 def NAME#32mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi32, opnode>;
969 def NAME#64mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi64, opnode>;
1012 multiclass ArithBinOp_RFF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
[all …]
DX86FastISel.cpp2889 unsigned BaseOpc, CondCode; in fastLowerIntrinsicCall() local
2893 BaseOpc = ISD::ADD; CondCode = X86::COND_O; break; in fastLowerIntrinsicCall()
2895 BaseOpc = ISD::ADD; CondCode = X86::COND_B; break; in fastLowerIntrinsicCall()
2897 BaseOpc = ISD::SUB; CondCode = X86::COND_O; break; in fastLowerIntrinsicCall()
2899 BaseOpc = ISD::SUB; CondCode = X86::COND_B; break; in fastLowerIntrinsicCall()
2901 BaseOpc = X86ISD::SMUL; CondCode = X86::COND_O; break; in fastLowerIntrinsicCall()
2903 BaseOpc = X86ISD::UMUL; CondCode = X86::COND_O; break; in fastLowerIntrinsicCall()
2919 if (CI->isOne() && (BaseOpc == ISD::ADD || BaseOpc == ISD::SUB) && in fastLowerIntrinsicCall()
2923 bool IsDec = BaseOpc == ISD::SUB; in fastLowerIntrinsicCall()
2928 ResultReg = fastEmit_ri(VT, VT, BaseOpc, LHSReg, LHSIsKill, in fastLowerIntrinsicCall()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Utils/
DAMDGPUBaseInfo.h278 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
296 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
DAMDGPUBaseInfo.cpp162 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements) { in getMTBUFOpcode() argument
163 const MTBUFInfo *Info = getMTBUFInfoFromBaseOpcodeAndElements(BaseOpc, Elements); in getMTBUFOpcode()
192 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements) { in getMUBUFOpcode() argument
193 const MUBUFInfo *Info = getMUBUFInfoFromBaseOpcodeAndElements(BaseOpc, Elements); in getMUBUFOpcode()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp699 int BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2ADDspImm in CreateLoadStoreMulti() local
711 BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2SUBspImm in CreateLoadStoreMulti()
734 (BaseOpc == ARM::tADDi8 || BaseOpc == ARM::tSUBi8)) { in CreateLoadStoreMulti()
752 if (BaseOpc == ARM::tADDrSPi) { in CreateLoadStoreMulti()
754 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase) in CreateLoadStoreMulti()
759 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase) in CreateLoadStoreMulti()
765 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase) in CreateLoadStoreMulti()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp2763 unsigned BaseOpc = BO.first.getOpcode(); in LowerUnalignedLoad() local
2764 if (BaseOpc == HexagonISD::VALIGNADDR && BO.second % LoadLen == 0) in LowerUnalignedLoad()
2772 SDValue BaseNoOff = (BaseOpc != HexagonISD::VALIGNADDR) in LowerUnalignedLoad()