| /third_party/mindspore/mindspore/lite/tools/converter/parser/caffe/ |
| D | caffe_pooling_parser.cc | 95 mindspore::RoundMode roundMode = mindspore::RoundMode::CEIL; in ParseRoundMode()
100 roundMode = mindspore::RoundMode::CEIL; in ParseRoundMode()
103 roundMode = poolingParam.ceil_mode() ? mindspore::RoundMode::CEIL : mindspore::RoundMode::FLOOR; in ParseRoundMode()
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| /third_party/mindspore/mindspore/lite/schema/ |
| D | ops_types.fbs | 37 CEIL = 4
116 CEIL = 1
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| D | ops_v0.fbs | 42 CEIL = 4
119 CEIL = 1
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| /third_party/mindspore/mindspore/lite/tools/converter/parser/onnx/ |
| D | onnx_pool_parser.cc | 71 round_mode = mindspore::RoundMode::CEIL; in Parse()
145 round_mode = mindspore::RoundMode::CEIL; in Parse()
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| D | onnx_resize_parser.cc | 66 {"ceil", mindspore::NearestMode::CEIL}, in Parse()
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| /third_party/mindspore/mindspore/core/utils/ |
| D | check_convert_utils.h | 106 CEIL = 1, enumerator
124 … NearestMode : int64_t { NORMAL = 0, ROUND_HALF_DOWN = 1, ROUND_HALF_UP = 2, FLOOR = 3, CEIL = 4 }; enumerator
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| /third_party/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_opcode_tmp.h | 107 OP11(CEIL)
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| D | tgsi_info_opcodes.h | 84 OPCODE(1, 1, COMP, CEIL)
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| D | tgsi_lowering.c | 1478 OPCS(CEIL) || in tgsi_transform_lowering()
1536 if (OPCS(CEIL)) { in tgsi_transform_lowering()
1537 newlen += CEIL_GROW * OPCS(CEIL); in tgsi_transform_lowering()
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| /third_party/mindspore/mindspore/lite/tools/converter/acl/mapper/ |
| D | primitive_mapper.cc | 127 bool ceil_mode = run_mode == RoundMode::CEIL; in AdjustOnnxPoolAttr()
|
| /third_party/mindspore/mindspore/ccsrc/frontend/parallel/auto_parallel/rec_core/ |
| D | rec_parse_graph.h | 116 {CEIL, OperatorType::kRecElmWiseOp},
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| /third_party/mesa3d/src/gallium/drivers/swr/rasterizer/common/ |
| D | simdlib_types.hpp | 127 CEIL = static_cast<int>(TO_POS_INF) | static_cast<int>(RAISE_EXC), enumerator
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| D | simdlib_interface.hpp | 74 CEIL = static_cast<int>(TO_POS_INF) | static_cast<int>(RAISE_EXC),
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| /third_party/mesa3d/src/gallium/drivers/etnaviv/ |
| D | etnaviv_compiler_nir_emit.c | 71 OP(fsign, SIGN, X_X_0), OP(ffloor, FLOOR, X_X_0), OP(fceil, CEIL, X_X_0),
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| D | etnaviv_disasm.c | 502 OPC(CEIL),
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrFloat.td | 64 defm CEIL : UnaryFP<fceil, "ceil", 0x8d, 0x9b>;
|
| /third_party/glib/glib/gnulib/ |
| D | meson.build | 19 'CEIL',
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| /third_party/mindspore/mindspore/ccsrc/frontend/parallel/ops_info/ |
| D | ops_utils.h | 346 constexpr char CEIL[] = "Ceil"; variable
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| /third_party/mindspore/mindspore/ccsrc/frontend/parallel/ |
| D | step_auto_parallel.cc | 141 ATAN, ATANH, CEIL, in IsElementWiseOperator()
169 …_LOOKUP, FUSE_BATCH_NORM_EX, SPLIT, BROADCAST_TO, ABS, ACOSH, ASIN, ASINH, ATAN, ATANH, CEIL, COSH, in IsSplittableOperator()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | R600Instructions.td | 796 def CEIL : R600_1OP_Helper <0x12, "CEIL", fceil>;
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| /third_party/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_from_tgsi.cpp | 784 NV50_IR_OPCODE_CASE(CEIL, CEIL); in translateOpcode()
855 NV50_IR_OPCODE_CASE(DCEIL, CEIL); in translateOpcode()
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| /third_party/mindspore/mindspore/lite/tools/converter/parser/tflite/ |
| D | schema.fbs | 329 CEIL = 104,
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| /third_party/mindspore/third_party/proto/tensorflow/lite/ |
| D | schema.fbs | 329 CEIL = 104,
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| D | schema_2.4.1.fbs | 331 CEIL = 104,
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| /third_party/skia/third_party/externals/opengl-registry/extensions/NV/ |
| D | NV_gpu_program5.txt | 378 | "CEIL"
673 CEIL 40 6 6 X X X F v vf ceiling
874 CEIL Inexact conversion results round to larger value
977 For the CVT (data type conversion) instruction, the "ROUND", "CEIL",
1682 chosen according to the rounding instruction modifier. If "CEIL" or "FLR"
1696 values, even if a rounding modifier such as CEIL or FLR is specified.
|