Searched refs:CIK_UCONFIG_REG_OFFSET (Results 1 – 8 of 8) sorted by relevance
134 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_seq()138 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2); in radeon_set_uconfig_reg_seq()144 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_seq_perfctr()148 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2); in radeon_set_uconfig_reg_seq_perfctr()162 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_idx()172 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28)); in radeon_set_uconfig_reg_idx()179 assert(reg < CIK_UCONFIG_REG_OFFSET); in radeon_set_privileged_config_reg()
186 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_seq()189 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2); in radeon_set_uconfig_reg_seq()202 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_idx()205 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28)); in radeon_set_uconfig_reg_idx()
33 #define CIK_UCONFIG_REG_OFFSET 0x00030000 macro
127 assert((reg) >= CIK_UCONFIG_REG_OFFSET && (reg) < CIK_UCONFIG_REG_END); \129 radeon_emit(((reg) - CIK_UCONFIG_REG_OFFSET) >> 2); \144 assert((reg) >= CIK_UCONFIG_REG_OFFSET && (reg) < CIK_UCONFIG_REG_END); \151 radeon_emit(((reg) - CIK_UCONFIG_REG_OFFSET) >> 2 | ((idx) << 28)); \261 assert((reg) < CIK_UCONFIG_REG_OFFSET); \
69 } else if (reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END) { in si_pm4_set_reg()71 reg -= CIK_UCONFIG_REG_OFFSET; in si_pm4_set_reg()
44 offset = CIK_UCONFIG_REG_OFFSET; in si_build_load_reg()
36 #define CIK_UCONFIG_REG_OFFSET 0x00030000 macro44 #define SI_UCONFIG_REG_SPACE_SIZE (CIK_UCONFIG_REG_END - CIK_UCONFIG_REG_OFFSET)
289 ac_parse_set_reg_packet(f, count, CIK_UCONFIG_REG_OFFSET, ib); in ac_parse_packet3()