| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLoweringHVX.cpp | 96 setOperationAction(ISD::CONCAT_VECTORS, T, Custom); in initializeHVXLowering()
130 setOperationAction(ISD::CONCAT_VECTORS, T, Custom); in initializeHVXLowering()
187 setOperationAction(ISD::CONCAT_VECTORS, BoolV, Custom); in initializeHVXLowering()
261 return DAG.getNode(ISD::CONCAT_VECTORS, dl, typeJoin(ty(Ops)), in opJoin()
909 SDValue InLo = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {SubV, V1}); in insertHvxSubvectorReg()
910 SDValue InHi = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {V0, SubV}); in insertHvxSubvectorReg()
956 SDValue InLo = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {SingleV, V1}); in insertHvxSubvectorReg()
957 SDValue InHi = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {V0, SingleV}); in insertHvxSubvectorReg()
1044 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, V0, V1); in LowerHvxBuildVector()
1112 SDValue V0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfTy, in LowerHvxConcatVectors()
[all …]
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| D | HexagonISelLowering.cpp | 1493 ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE in HexagonTargetLowering()
1542 setOperationAction(ISD::CONCAT_VECTORS, NativeVT, Custom); in HexagonTargetLowering()
2903 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); in LowerOperation()
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| D | HexagonISelDAGToDAGHVX.cpp | 1430 LV = DAG.getNode(ISD::CONCAT_VECTORS, dl, ResTy, {L0, L1}); in scalarizeShuffle()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 583 case ISD::CONCAT_VECTORS: in ScalarizeVectorOperand()
832 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break; in SplitVectorResult()
1102 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps); in SplitVecRes_CONCAT_VECTORS()
1105 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps); in SplitVecRes_CONCAT_VECTORS()
1399 ISD::CONCAT_VECTORS, dl, OtherVT, in SplitVecRes_OverflowOp()
1929 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break; in SplitVectorOperand()
2052 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect); in SplitVecOp_VSELECT()
2127 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); in SplitVecOp_UnaryOp()
2232 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), N->getValueType(0), Lo, Hi); in SplitVecOp_ExtVecInRegOp()
2300 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, MGT->getValueType(0), Lo, in SplitVecOp_MGATHER()
[all …]
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| D | DAGCombiner.cpp | 1601 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); in visit()
8700 assert(LHS.getOpcode() == ISD::CONCAT_VECTORS && in ConvertSelectToConcatVector()
8701 RHS.getOpcode() == ISD::CONCAT_VECTORS && in ConvertSelectToConcatVector()
8741 ISD::CONCAT_VECTORS, DL, VT, in ConvertSelectToConcatVector()
8969 if (N1.getOpcode() == ISD::CONCAT_VECTORS && in visitVSELECT()
8970 N2.getOpcode() == ISD::CONCAT_VECTORS && in visitVSELECT()
9326 SDValue NewValue = DAG.getNode(ISD::CONCAT_VECTORS, DL, DstVT, Loads); in CombineExtLoad()
10912 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) { in visitTRUNCATE()
10948 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Opnds); in visitTRUNCATE()
15409 StoredVal = DAG.getNode(MemVT.isVector() ? ISD::CONCAT_VECTORS in MergeStoresOfConstantsOrVecElts()
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| D | SelectionDAGDumper.cpp | 282 case ISD::CONCAT_VECTORS: return "concat_vectors"; in getOperationName()
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| D | SelectionDAG.cpp | 2606 case ISD::CONCAT_VECTORS: { in computeKnownBits()
3933 case ISD::CONCAT_VECTORS: { in ComputeNumSignBits()
4561 case ISD::CONCAT_VECTORS: in getNode()
5163 case ISD::CONCAT_VECTORS: { in getNode()
5336 N1.getOpcode() == ISD::CONCAT_VECTORS && in getNode()
5437 if (N2C && N1.getOpcode() == ISD::CONCAT_VECTORS && in getNode()
5565 case ISD::CONCAT_VECTORS: { in getNode()
7359 case ISD::CONCAT_VECTORS: in getNode()
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| D | LegalizeIntegerTypes.cpp | 107 case ISD::CONCAT_VECTORS: in PromoteIntegerResult()
1034 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2); in PromoteIntRes_TRUNCATE()
1258 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break; in PromoteIntegerOperand()
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| D | LegalizeDAG.cpp | 3022 case ISD::CONCAT_VECTORS: in ExpandNode()
4561 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewOps); in PromoteNode()
4683 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewElts); in PromoteNode()
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| D | SelectionDAGBuilder.cpp | 422 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS in getCopyFromPartsVector()
3651 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps)); in visitShuffleVector()
3669 Src1 = DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps1); in visitShuffleVector()
3670 Src2 = DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps2); in visitShuffleVector()
5538 case ISD::CONCAT_VECTORS: in getUnderlyingArgRegs()
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| D | TargetLowering.cpp | 975 case ISD::CONCAT_VECTORS: { in SimplifyDemandedBits()
2309 case ISD::CONCAT_VECTORS: { in SimplifyDemandedVectorElts()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 399 CONCAT_VECTORS, enumerator
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 1351 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in X86TargetLowering()
1430 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in X86TargetLowering()
1547 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom); in X86TargetLowering()
1548 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom); in X86TargetLowering()
1549 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom); in X86TargetLowering()
1550 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom); in X86TargetLowering()
1751 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom); in X86TargetLowering()
1752 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom); in X86TargetLowering()
1782 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i16, Custom); in X86TargetLowering()
1783 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i8, Custom); in X86TargetLowering()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 278 setOperationAction(ISD::CONCAT_VECTORS, MVT::v3i32, Custom); in AMDGPUTargetLowering()
279 setOperationAction(ISD::CONCAT_VECTORS, MVT::v3f32, Custom); in AMDGPUTargetLowering()
280 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); in AMDGPUTargetLowering()
281 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom); in AMDGPUTargetLowering()
282 setOperationAction(ISD::CONCAT_VECTORS, MVT::v5i32, Custom); in AMDGPUTargetLowering()
283 setOperationAction(ISD::CONCAT_VECTORS, MVT::v5f32, Custom); in AMDGPUTargetLowering()
284 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom); in AMDGPUTargetLowering()
285 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); in AMDGPUTargetLowering()
1131 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); in LowerOperation()
1440 Join = DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad); in SplitVectorLoad()
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| D | SIISelLowering.cpp | 276 case ISD::CONCAT_VECTORS: in SITargetLowering()
538 case ISD::CONCAT_VECTORS: in SITargetLowering()
3985 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi); in splitUnaryVectorOp()
4008 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi); in splitBinaryVectorOp()
4031 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi); in splitTernaryVectorOp()
4975 return DAG.getNode(ISD::CONCAT_VECTORS, SL, ResultVT, Pieces); in lowerVECTOR_SHUFFLE()
5736 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Loads); in lowerSBuffer()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 648 setTargetDAGCombine(ISD::CONCAT_VECTORS); in AArch64TargetLowering()
902 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal); in addTypeForNEON()
3088 SDValue TruncExt = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i16, in LowerTruncateVectorStore()
6638 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
7027 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1); in tryFormConcatFromShuffle()
7165 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst); in GenerateTBL()
7173 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst); in GenerateTBL()
7282 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) { in LowerVECTOR_SHUFFLE()
10422 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy, in performConcatVectorsCombine()
11200 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); in performExtendCombine()
[all …]
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| D | AArch64InstrFormats.td | 8788 // intrinsic, represented by CONCAT_VECTORS.
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 184 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal); in addTypeForNEON()
412 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in addMVEVectorTypes()
7344 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lower, Upper); in LowerBUILD_VECTOR()
7480 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8047 if (ST->hasNEON() && V1->getOpcode() == ISD::CONCAT_VECTORS && V2->isUndef()) { in LowerVECTOR_SHUFFLE()
8065 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Res.getValue(0), in LowerVECTOR_SHUFFLE()
8739 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerSDIV()
8776 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerUDIV()
9338 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG, Subtarget); in LowerOperation()
11172 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), ConcatVT, in AddCombineVUZPToVPADDL()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 638 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand); in initActions()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 645 def concat_vectors : SDNode<"ISD::CONCAT_VECTORS",
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 990 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f64, Expand); in PPCTargetLowering()
1038 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f32, Expand); in PPCTargetLowering()
1079 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4i1, Expand); in PPCTargetLowering()
7988 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WideVT, Ops); in widenVec()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 2189 case ISD::CONCAT_VECTORS: in LowerOperation()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenDAGISel.inc | 63895 /*140977*/ /*SwitchOpcode*/ 20|128,1/*148*/, TARGET_VAL(ISD::CONCAT_VECTORS),// ->141129
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