| /third_party/mesa3d/src/intel/compiler/ |
| D | brw_vec4_builder.h | 406 ALU3(CSEL) in ALU2_ACC()
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| D | brw_fs_builder.h | 720 CSEL(const dst_reg &dst, const src_reg &src0, const src_reg &src1, in CSEL() function
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| D | brw_eu.h | 245 ALU3(CSEL) in ALU2()
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| D | brw_eu_emit.c | 1096 ALU3(CSEL) in ALU1()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 1109 case AArch64ISD::CSEL: { in computeKnownBitsForTargetNode()
1242 case AArch64ISD::CSEL: return "AArch64ISD::CSEL"; in getTargetNodeName()
2366 return DAG.getNode(AArch64ISD::CSEL, dl, Op.getValueType(), TVal, FVal, in LowerXOR()
2416 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal, in LowerXOR()
2478 Overflow = DAG.getNode(AArch64ISD::CSEL, dl, MVT::i32, FVal, TVal, in LowerXALUO()
5256 SDValue Res = DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp); in LowerSETCC()
5283 Res = DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp); in LowerSETCC()
5293 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp); in LowerSETCC()
5296 Res = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp); in LowerSETCC()
5329 unsigned Opcode = AArch64ISD::CSEL; in LowerSELECT_CC()
[all …]
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| D | AArch64ISelLowering.h | 43 CSEL, enumerator
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| D | AArch64SchedThunderX2T99.td | 431 "CCMP(W|X)(i|r)", "CSEL(W|X)r",
453 "CCMP(W|X)(i|r)", "CSEL(W|X)r",
472 "CCMP(W|X)(i|r)", "CSEL(W|X)r",
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| D | AArch64SchedCyclone.td | 146 // CSEL,CSINC,CSINV,CSNEG
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| D | AArch64SchedFalkorDetails.td | 894 def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^(CSEL|CSINC|CSINV|CSNEG)(W|X)r$")>;
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| D | AArch64SchedKryoDetails.td | 543 (instregex "CSEL(W|X)r")>;
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| D | AArch64InstrInfo.td | 400 def AArch64csel : SDNode<"AArch64ISD::CSEL", SDT_AArch64CSel>;
1795 defm CSEL : CondSelect<0, 0b00, "csel">;
3567 // CSEL instructions providing f128 types need to be handled by a
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| /third_party/mesa3d/src/intel/tools/ |
| D | i965_lex.l | 72 csel { yylval.integer = BRW_OPCODE_CSEL; return CSEL; }
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| D | i965_gram.y | 387 %token <integer> CALL CALLA CASE CBIT CMP CMPN CONT CSEL
913 CSEL
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| /third_party/pcre2/pcre2/src/sljit/ |
| D | sljitNativeARM_64.c | 84 #define CSEL 0x9a800000 macro
1869 return push_inst(compiler, (CSEL ^ inv_bits) | (cc << 12) | RD(dst_reg) | RN(dst_reg) | RM(src)); in sljit_emit_cmov()
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| /third_party/mesa3d/docs/relnotes/ |
| D | 20.1.0.rst | 413 - pan/bi: Add CSEL condition
597 - pan/bi: Match CSEL argument order with hw
608 - pan/bit: Add CSEL to interpreter
735 - pan/bi: Add CSEL.64 opcode
739 - pan/bi: Add CSEL.8 opcode
2226 - intel/compiler: CSEL can do saturate
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| D | 20.0.0.rst | 1622 - Revert "i965/fs: Merge CMP and SEL into CSEL on Gen8+"
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| D | 20.2.0.rst | 503 - pan/bi: Add CSEL.16 packing tests
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| D | 21.2.0.rst | 441 - pan/bi: Emit int CSEL instead of float by default
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 419 // CSEL aliases inverted predicate
751 // CSEL). Setting Unpredictable{15} = 1 here would reintroduce
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