| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | LiveRangeShrink.cpp | 166 const MachineOperand *DefMO = nullptr; in runOnMachineFunction() local
187 if (DefMO) { in runOnMachineFunction()
191 DefMO = &MO; in runOnMachineFunction()
192 } else if (MRI.hasOneNonDBGUse(Reg) && MRI.hasOneDef(Reg) && DefMO && in runOnMachineFunction()
193 MRI.getRegClass(DefMO->getReg()) == in runOnMachineFunction()
218 if (DefMO && Insert && NumEligibleUse > 1 && Barrier <= IOM[Insert]) { in runOnMachineFunction()
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| D | MachineLICM.cpp | 1166 MachineOperand &DefMO = MI.getOperand(i); in IsCheapInstruction() local
1167 if (!DefMO.isReg() || !DefMO.isDef()) in IsCheapInstruction()
1170 Register Reg = DefMO.getReg(); in IsCheapInstruction()
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| D | ModuloSchedule.cpp | 1595 for (MachineOperand &DefMO : MI->defs()) { in filterInstructions()
1597 for (MachineInstr &UseMI : MRI.use_instructions(DefMO.getReg())) { in filterInstructions()
1606 Sub.first->substituteRegister(DefMO.getReg(), Sub.second, /*SubIdx=*/0, in filterInstructions()
1905 for (MachineOperand &DefMO : MI->defs()) { in rewriteUsesOf()
1907 for (MachineInstr &UseMI : MRI.use_instructions(DefMO.getReg())) { in rewriteUsesOf()
1916 Sub.first->substituteRegister(DefMO.getReg(), Sub.second, /*SubIdx=*/0, in rewriteUsesOf()
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| D | MachineInstr.cpp | 1051 MachineOperand &DefMO = getOperand(DefIdx); in tieOperands() local
1053 assert(DefMO.isDef() && "DefIdx must be a def operand"); in tieOperands()
1055 assert(!DefMO.isTied() && "Def is already tied to another use"); in tieOperands()
1069 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax); in tieOperands()
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| D | RegisterCoalescer.cpp | 1321 MachineOperand &DefMO = NewMI.getOperand(0); in reMaterializeTrivialDef() local
1322 if (DefMO.getSubReg() == DstIdx) { in reMaterializeTrivialDef()
1331 DefMO.setSubReg(0); in reMaterializeTrivialDef()
1332 DefMO.setIsUndef(false); // Only subregs can have def+undef. in reMaterializeTrivialDef()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyExplicitLocals.cpp | 177 for (MachineOperand &DefMO : Def->explicit_uses()) { in findStartOfTree()
178 if (!DefMO.isReg()) in findStartOfTree()
180 return findStartOfTree(DefMO, MRI, MFI); in findStartOfTree()
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| D | WebAssemblyRegStackify.cpp | 612 MachineOperand &DefMO = Def->getOperand(0); in moveAndTeeForMultiUse() local
616 .addReg(DefReg, getUndefRegState(DefMO.isDead())); in moveAndTeeForMultiUse()
618 DefMO.setReg(DefReg); in moveAndTeeForMultiUse()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIPeepholeSDWA.cpp | 321 for (auto &DefMO : DefInstr->defs()) { in findSingleRegDef() local
322 if (DefMO.isReg() && DefMO.getReg() == Reg->getReg()) in findSingleRegDef()
323 return &DefMO; in findSingleRegDef()
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| D | SIInsertWaitcnts.cpp | 623 MachineOperand &DefMO = Inst.getOperand(I); in updateByEvent() local
624 if (DefMO.isReg() && DefMO.isDef() && in updateByEvent()
625 TRI->isVGPR(MRIA, DefMO.getReg())) { in updateByEvent()
626 setRegScore(TRI->getEncodingValue(DefMO.getReg()), EXP_CNT, in updateByEvent()
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| D | SIInstrInfo.h | 712 const MachineOperand &DefMO) const { in isInlineConstant() argument
719 return isInlineConstant(DefMO, MI.getDesc().OpInfo[OpIdx]); in isInlineConstant()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 374 const MachineOperand &DefMO, unsigned Reg,
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| D | ARMBaseInstrInfo.cpp | 4257 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); in getOperandLatency() local
4258 Register Reg = DefMO.getReg(); in getOperandLatency()
4280 ItinData, *ResolvedDefMI, DefIdx, ResolvedDefMI->getDesc(), DefAdj, DefMO, in getOperandLatency()
4287 const MachineOperand &DefMO, unsigned Reg, const MachineInstr &UseMI, in getOperandLatencyImpl() argument
4315 if (DefMO.isImplicit() || UseMI.getOperand(UseIdx).isImplicit()) in getOperandLatencyImpl()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 4102 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); in getOperandLatency() local
4104 if (DefMO.isReg() && Register::isPhysicalRegister(DefMO.getReg())) { in getOperandLatency()
4105 if (DefMO.isImplicit()) { in getOperandLatency()
4106 for (MCSuperRegIterator SR(DefMO.getReg(), &HRI); SR.isValid(); ++SR) { in getOperandLatency()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 185 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); in getOperandLatency() local
186 Register Reg = DefMO.getReg(); in getOperandLatency()
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