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Searched refs:DestVT (Results 1 – 19 of 19) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsFastISel.cpp187 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
188 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
191 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
193 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
194 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
196 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1001 EVT DestVT = TLI.getValueType(DL, I->getType(), true); in selectFPExt() local
1003 if (SrcVT != MVT::f32 || DestVT != MVT::f64) in selectFPExt()
1080 EVT DestVT = TLI.getValueType(DL, I->getType(), true); in selectFPTrunc() local
1082 if (SrcVT != MVT::f64 || DestVT != MVT::f32) in selectFPTrunc()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp172 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
961 EVT DestVT = TLI.getValueType(DL, I->getType(), true); in SelectFPExt() local
963 if (SrcVT != MVT::f32 || DestVT != MVT::f64) in SelectFPExt()
979 EVT DestVT = TLI.getValueType(DL, I->getType(), true); in SelectFPTrunc() local
981 if (SrcVT != MVT::f64 || DestVT != MVT::f32) in SelectFPTrunc()
1270 EVT DestVT = TLI.getValueType(DL, I->getType(), true); in SelectBinaryIntOp() local
1274 if (DestVT != MVT::i16 && DestVT != MVT::i8) in SelectBinaryIntOp()
1442 MVT DestVT = VA.getLocVT(); in processCallArgs() local
1444 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass; in processCallArgs()
1446 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/false)) in processCallArgs()
[all …]
DPPCISelLowering.h862 bool isFPExtFree(EVT DestVT, EVT SrcVT) const override;
DPPCISelLowering.cpp8472 const SDLoc &dl, EVT DestVT = MVT::Other) { in BuildIntrinsicOp() argument
8473 if (DestVT == MVT::Other) DestVT = Op.getValueType(); in BuildIntrinsicOp()
8474 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, in BuildIntrinsicOp()
8482 EVT DestVT = MVT::Other) { in BuildIntrinsicOp() argument
8483 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); in BuildIntrinsicOp()
8484 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, in BuildIntrinsicOp()
8492 EVT DestVT = MVT::Other) { in BuildIntrinsicOp() argument
8493 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); in BuildIntrinsicOp()
8494 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, in BuildIntrinsicOp()
15220 bool PPCTargetLowering::isFPExtFree(EVT DestVT, EVT SrcVT) const { in isFPExtFree() argument
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp233 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
234 unsigned emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
2873 MVT DestVT; in selectFPToInt() local
2874 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector()) in selectFPToInt()
2888 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr; in selectFPToInt()
2890 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr; in selectFPToInt()
2893 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr; in selectFPToInt()
2895 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr; in selectFPToInt()
2898 DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass); in selectFPToInt()
2906 MVT DestVT; in selectIntToFP() local
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DAArch64ISelLowering.cpp6631 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts); in ReconstructShuffle() local
6638 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
6654 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
6660 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
6665 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
6668 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
6672 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1, in ReconstructShuffle()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMFastISel.cpp205 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
1750 EVT DestVT = TLI.getValueType(DL, I->getType(), true); in SelectBinaryIntOp() local
1754 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1) in SelectBinaryIntOp()
1965 MVT DestVT = VA.getLocVT(); in ProcessCallArgs() local
1966 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false); in ProcessCallArgs()
1968 ArgVT = DestVT; in ProcessCallArgs()
1974 MVT DestVT = VA.getLocVT(); in ProcessCallArgs() local
1975 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true); in ProcessCallArgs()
1977 ArgVT = DestVT; in ProcessCallArgs()
2053 MVT DestVT = RVLocs[0].getValVT(); in FinishCall() local
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DARMISelLowering.cpp7472 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts); in ReconstructShuffle() local
7480 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
7496 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
7502 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
7507 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
7510 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
7513 Src.ShuffleVec = DAG.getNode(ARMISD::VEXT, dl, DestVT, VEXTSrc1, in ReconstructShuffle()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeDAG.cpp161 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
163 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
877 EVT DestVT = Node->getValueType(0); in LegalizeLoadOps() local
878 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) { in LegalizeLoadOps()
904 EVT IDestVT = DestVT.changeTypeToInteger(); in LegalizeLoadOps()
909 Value = DAG.getNode(ISD::FP16_TO_FP, dl, DestVT, Result); in LegalizeLoadOps()
1746 EVT DestVT, const SDLoc &dl) { in EmitStackConvert() argument
1747 return EmitStackConvert(SrcOp, SlotVT, DestVT, dl, DAG.getEntryNode()); in EmitStackConvert()
1751 EVT DestVT, const SDLoc &dl, in EmitStackConvert() argument
1765 unsigned DestSize = DestVT.getSizeInBits(); in EmitStackConvert()
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DLegalizeTypes.cpp858 EVT DestVT) { in CreateStackStoreLoad() argument
862 SDValue StackPtr = DAG.CreateStackTemporary(Op.getValueType(), DestVT); in CreateStackStoreLoad()
867 return DAG.getLoad(DestVT, dl, Store, StackPtr, MachinePointerInfo()); in CreateStackStoreLoad()
DSelectionDAGBuilder.cpp3256 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), in visitICmp() local
3258 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode)); in visitICmp()
3275 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), in visitFCmp() local
3277 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition)); in visitFCmp()
3419 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), in visitTrunc() local
3421 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N)); in visitTrunc()
3428 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), in visitZExt() local
3430 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N)); in visitZExt()
3437 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), in visitSExt() local
3439 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N)); in visitSExt()
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DLegalizeVectorTypes.cpp345 EVT DestVT = N->getValueType(0).getVectorElementType(); in ScalarizeVecRes_UnaryOp() local
364 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op); in ScalarizeVecRes_UnaryOp()
1723 EVT DestVT = N->getValueType(0); in SplitVecRes_ExtendOp() local
1725 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT); in SplitVecRes_ExtendOp()
1742 SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) { in SplitVecRes_ExtendOp()
DLegalizeTypes.h208 SDValue CreateStackStoreLoad(SDValue Op, EVT DestVT);
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DTargetLoweringBase.cpp974 MVT DestVT = TLI->getRegisterType(NewVT); in getVectorTypeBreakdownMVT() local
975 RegisterVT = DestVT; in getVectorTypeBreakdownMVT()
976 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. in getVectorTypeBreakdownMVT()
977 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); in getVectorTypeBreakdownMVT()
1424 MVT DestVT = getRegisterType(Context, NewVT); in getVectorTypeBreakdown() local
1425 RegisterVT = DestVT; in getVectorTypeBreakdown()
1432 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. in getVectorTypeBreakdown()
1433 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); in getVectorTypeBreakdown()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DTargetLowering.h2086 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { in AddPromotedToType() argument
2087 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; in AddPromotedToType()
2092 void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { in setOperationPromotedToType() argument
2094 AddPromotedToType(Opc, OrigVT, DestVT); in setOperationPromotedToType()
2476 virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const { in isFPExtFree() argument
2477 assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() && in isFPExtFree()
2486 EVT DestVT, EVT SrcVT) const { in isFPExtFoldable() argument
2487 assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() && in isFPExtFoldable()
2489 return isFPExtFree(DestVT, SrcVT); in isFPExtFoldable()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp820 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const { in isNarrowingProfitable()
827 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32; in isNarrowingProfitable()
2507 EVT DestVT = Op.getValueType(); in LowerUINT_TO_FP() local
2512 if (DestVT == MVT::f16) in LowerUINT_TO_FP()
2518 return DAG.getNode(ISD::UINT_TO_FP, DL, DestVT, Ext); in LowerUINT_TO_FP()
2523 if (Subtarget->has16BitInsts() && DestVT == MVT::f16) { in LowerUINT_TO_FP()
2534 if (DestVT == MVT::f32) in LowerUINT_TO_FP()
2537 assert(DestVT == MVT::f64); in LowerUINT_TO_FP()
2543 EVT DestVT = Op.getValueType(); in LowerSINT_TO_FP() local
2549 if (DestVT == MVT::f16) in LowerSINT_TO_FP()
[all …]
DSIISelLowering.h225 bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT,
DSIISelLowering.cpp781 EVT DestVT, EVT SrcVT) const { in isFPExtFoldable() argument
784 DestVT.getScalarType() == MVT::f32 && in isFPExtFoldable()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86ISelLowering.cpp18651 MVT DestVT = Cast.getSimpleValueType(); in vectorizeExtractedCast() local
18661 MVT ToVT = MVT::getVectorVT(DestVT, NumEltsInXMM); in vectorizeExtractedCast()
18681 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, DestVT, VCast, in vectorizeExtractedCast()
22518 MVT DestVT = VT == MVT::v2i64 ? MVT::v4i32 : VT; in LowerEXTEND_VECTOR_INREG() local
22520 unsigned DestWidth = DestVT.getScalarSizeInBits(); in LowerEXTEND_VECTOR_INREG()
22524 unsigned DestElts = DestVT.getVectorNumElements(); in LowerEXTEND_VECTOR_INREG()
22533 Curr = DAG.getBitcast(DestVT, Curr); in LowerEXTEND_VECTOR_INREG()
22536 SignExt = DAG.getNode(X86ISD::VSRAI, dl, DestVT, Curr, in LowerEXTEND_VECTOR_INREG()