Searched refs:DstHi (Results 1 – 6 of 6) sorted by relevance
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEFrameLowering.cpp | 269 Register DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi); in expandCopyACC() local
276 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi) in expandCopyACC()
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| D | MipsSEInstrInfo.cpp | 734 Register DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi); in expandPseudoMTLoHi() local
736 HiInst.addReg(DstHi, RegState::Define); in expandPseudoMTLoHi()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 348 Register DstHi = MRI->createVirtualRegister(&HalfRC); in selectG_ADD_SUB() local
354 BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADDC_U32), DstHi) in selectG_ADD_SUB()
365 MachineInstr *Addc = BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_ADDC_U32_e64), DstHi) in selectG_ADD_SUB()
379 .addReg(DstHi) in selectG_ADD_SUB()
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| D | SIInstrInfo.cpp | 1430 Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo() local
1440 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi) in expandPostRAPseudo()
1448 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi) in expandPostRAPseudo()
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| D | SIISelLowering.cpp | 3766 Register DstHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in EmitInstrWithCustomInserter() local
3778 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstHi) in EmitInstrWithCustomInserter()
3788 .addReg(DstHi) in EmitInstrWithCustomInserter()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 1836 Register DstHi = HRI.getSubReg(DstR, Hexagon::vsub_hi); in expandLoadVec2() local
1861 BuildMI(B, It, DL, HII.get(LoadOpc), DstHi) in expandLoadVec2()
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