Searched refs:DstLo (Results 1 – 6 of 6) sorted by relevance
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEFrameLowering.cpp | 268 Register DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo); in expandCopyACC() local
273 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo) in expandCopyACC()
|
| D | MipsSEInstrInfo.cpp | 733 Register DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandPseudoMTLoHi() local
735 LoInst.addReg(DstLo, RegState::Define); in expandPseudoMTLoHi()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 347 Register DstLo = MRI->createVirtualRegister(&HalfRC); in selectG_ADD_SUB() local
351 BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADD_U32), DstLo) in selectG_ADD_SUB()
360 BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_ADD_I32_e64), DstLo) in selectG_ADD_SUB()
377 .addReg(DstLo) in selectG_ADD_SUB()
|
| D | SIInstrInfo.cpp | 1429 Register DstLo = RI.getSubReg(Dst, AMDGPU::sub0); in expandPostRAPseudo() local
1437 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo) in expandPostRAPseudo()
1445 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo) in expandPostRAPseudo()
|
| D | SIISelLowering.cpp | 3765 Register DstLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in EmitInstrWithCustomInserter() local
3772 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstLo) in EmitInstrWithCustomInserter()
3786 .addReg(DstLo) in EmitInstrWithCustomInserter()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 1837 Register DstLo = HRI.getSubReg(DstR, Hexagon::vsub_lo); in expandLoadVec2() local
1853 BuildMI(B, It, DL, HII.get(LoadOpc), DstLo) in expandLoadVec2()
|