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Searched refs:FINCSTP (Results 1 – 16 of 16) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86ScheduleZnver2.td911 // FINCSTP FDECSTP.
912 def : InstRW<[Zn2WriteFPU3], (instrs FINCSTP, FDECSTP)>;
DX86ScheduleZnver1.td911 // FINCSTP FDECSTP.
912 def : InstRW<[ZnWriteFPU3], (instrs FINCSTP, FDECSTP)>;
DX86ScheduleAtom.td549 def : InstRW<[AtomWrite01_1], (instrs FDECSTP, FFREE, FFREEP, FINCSTP, WAIT,
DX86SchedSandyBridge.td596 def: InstRW<[SBWriteResGroup2], (instrs FDECSTP, FINCSTP, FFREE, FFREEP, FNOP,
DX86InstrFPStack.td736 def FINCSTP : I<0xD9, MRM_F7, (outs), (ins), "fincstp", []>;
DX86SchedBroadwell.td644 def: InstRW<[BWWriteResGroup5], (instrs FINCSTP, FNOP)>;
DX86SchedHaswell.td907 def: InstRW<[HWWriteResGroup6], (instrs FINCSTP, FNOP)>;
DX86SchedSkylakeClient.td644 def: InstRW<[SKLWriteResGroup6], (instrs FINCSTP, FNOP)>;
DX86SchedSkylakeServer.td657 def: InstRW<[SKXWriteResGroup6], (instrs FINCSTP, FNOP)>;
/third_party/mesa3d/src/mesa/x86/
Dassyntax.h729 #define FINCSTP CHOICE(fincstp, fincstp, fincstp) macro
1442 #define FINCSTP fincstp macro
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenSubtargetInfo.inc6505 {DBGFIELD("FINCSTP") 1, false, false, 1, 1, 1, 1, 0, 0}, // #816
7882 {DBGFIELD("FINCSTP") 1, false, false, 96, 2, 2, 1, 0, 0}, // #816
9259 {DBGFIELD("FINCSTP") 1, false, false, 1173, 4, 1, 1, 0, 0}, // #816
10636 {DBGFIELD("FINCSTP") 1, false, false, 1, 1, 2, 1, 0, 0}, // #816
12013 {DBGFIELD("FINCSTP") 1, false, false, 2689, 5, 1, 1, 0, 0}, // #816
13390 {DBGFIELD("FINCSTP") 1, false, false, 3706, 5, 1, 1, 0, 0}, // #816
14767 {DBGFIELD("FINCSTP") 1, false, false, 1173, 4, 1, 1, 0, 0}, // #816
16144 {DBGFIELD("FINCSTP") 1, false, false, 3805, 2, 2, 1, 0, 0}, // #816
17521 {DBGFIELD("FINCSTP") 1, false, false, 2689, 5, 1, 1, 0, 0}, // #816
18898 {DBGFIELD("FINCSTP") 1, false, false, 4719, 7, 9, 1, 0, 0}, // #816
[all …]
DX86GenAsmWriter.inc2645 15954U, // FINCSTP
17896 0U, // FINCSTP
33147 0U, // FINCSTP
DX86GenAsmWriter1.inc2354 12741U, // FINCSTP
17605 0U, // FINCSTP
DX86GenDisassemblerTables.inc11279 /* FINCSTP */
77296 0x3d2, /* FINCSTP */
DX86GenAsmMatcher.inc8700 { 2483 /* fincstp */, X86::FINCSTP, Convert_NoOperands, AMFBS_None, { }, },
23272 { 2483 /* fincstp */, X86::FINCSTP, Convert_NoOperands, AMFBS_None, { }, },
DX86GenInstrInfo.inc993 FINCSTP = 978,
16093 FINCSTP = 816,
18678 …Effects), 0x3640000077ULL, nullptr, ImplicitList12, nullptr, -1 ,nullptr }, // Inst #978 = FINCSTP