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Searched refs:FMIN (Results 1 – 17 of 17) sorted by relevance

/third_party/gstreamer/gstplugins_good/gst/goom/
Dconfig_param.c46 FMIN (*p) = 0.0f; in goom_secure_f_param()
Dgoom_config_param.h92 #define FMIN(p) ((p).param.fval.min) macro
/third_party/mesa3d/src/gallium/drivers/vc4/
Dvc4_qpu.h196 A_ALU2(FMIN)
Dvc4_qpu_emit.c260 A(FMIN), in vc4_generate_code_block()
Dvc4_qir.h683 QIR_ALU2(FMIN) in QIR_ALU1()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h359 X86_INTRINSIC_DATA(avx_min_pd_256, INTR_TYPE_2OP, X86ISD::FMIN, 0),
360 X86_INTRINSIC_DATA(avx_min_ps_256, INTR_TYPE_2OP, X86ISD::FMIN, 0),
818 X86_INTRINSIC_DATA(avx512_min_pd_512, INTR_TYPE_2OP_SAE, X86ISD::FMIN, X86ISD::FMIN_SAE),
819 X86_INTRINSIC_DATA(avx512_min_ps_512, INTR_TYPE_2OP_SAE, X86ISD::FMIN, X86ISD::FMIN_SAE),
1013 X86_INTRINSIC_DATA(sse_min_ps, INTR_TYPE_2OP, X86ISD::FMIN, 0),
1043 X86_INTRINSIC_DATA(sse2_min_pd, INTR_TYPE_2OP, X86ISD::FMIN, 0),
DX86InstrFragmentsSIMD.td38 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
43 // Commutative and Associative FMIN and FMAX.
DX86ISelLowering.h238 FMAX, FMIN, enumerator
DREADME-SSE.txt332 specified. We should turn int_x86_sse_max_ss and X86ISD::FMIN etc. into other
DX86ISelLowering.cpp28801 case X86ISD::FMIN: in ReplaceNodeResults()
29660 case X86ISD::FMIN: return "X86ISD::FMIN"; in getTargetNodeName()
30046 case X86ISD::FMIN: in isBinOp()
37242 case X86ISD::FMIN: in scalarizeExtEltFP()
37949 Opcode = X86ISD::FMIN; in combineSelect()
37957 Opcode = X86ISD::FMIN; in combineSelect()
37967 Opcode = X86ISD::FMIN; in combineSelect()
38018 Opcode = X86ISD::FMIN; in combineSelect()
38024 Opcode = X86ISD::FMIN; in combineSelect()
38034 Opcode = X86ISD::FMIN; in combineSelect()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SchedA57.td465 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?(v2f32)")>;
467 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FMAX|FMIN)(NM)?(v4f32|v2f64)")>;
469 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?P(v2f32|v2i32)")>;
471 def : InstRW<[A57Write_9cyc_3V], (instregex "^(FMAX|FMIN)(NM)?P(v4f32|v2f64|v2i64)")>;
473 def : InstRW<[A57Write_10cyc_3V], (instregex "^(FMAX|FMIN)(NM)?Vv")>;
DAArch64InstrInfo.td3477 defm FMIN : TwoOperandFPData<0b0101, "fmin", fminimum>;
3863 defm FMIN : SIMDThreeSameVectorFP<0,1,0b110,"fmin", fminimum>;
/third_party/mesa3d/src/broadcom/compiler/
Dv3d_compiler.h1262 VIR_A_ALU2(FMIN) in VIR_A_ALU2()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.td839 defm FMIN : F3<"min", fminnum>;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenFastISel.inc11710 // FastEmit functions for X86ISD::FMIN.
15167 case X86ISD::FMIN: return fastEmit_X86ISD_FMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
/third_party/mesa3d/docs/relnotes/
D20.3.0.rst627 - pan/bi: Drop \*FMIN reference
D21.2.0.rst838 - pan/bi: Fuse abs into FCMP/FMIN/FMAX.v2f16