| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrHFP.td | 23 def LTDR : UnaryRR <"ltdr", 0x22, null_frag, FP64, FP64>;
32 def LEDR : UnaryRR <"ledr", 0x35, null_frag, FP32, FP64>;
34 def LDXR : UnaryRR <"ldxr", 0x25, null_frag, FP64, FP128>;
36 def LRER : UnaryRR <"lrer", 0x35, null_frag, FP32, FP64>;
37 def LRDR : UnaryRR <"lrdr", 0x25, null_frag, FP64, FP128>;
41 def LDER : UnaryRRE<"lder", 0xB324, null_frag, FP64, FP32>;
43 def LXDR : UnaryRRE<"lxdr", 0xB325, null_frag, FP128, FP64>;
45 def LDE : UnaryRXE<"lde", 0xED24, null_frag, FP64, 4>;
51 def CDFR : UnaryRRE<"cdfr", 0xB3B5, null_frag, FP64, GR32>;
55 def CDGR : UnaryRRE<"cdgr", 0xB3C5, null_frag, FP64, GR64>;
[all …]
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| D | SystemZInstrDFP.td | 23 def LTDTR : UnaryRRE<"ltdtr", 0xB3D6, null_frag, FP64, FP64>;
35 def LEDTR : TernaryRRFe<"ledtr", 0xB3D5, FP32, FP64>;
41 def LDETR : BinaryRRFd<"ldetr", 0xB3D4, FP64, FP32>;
42 def LXDTR : BinaryRRFd<"lxdtr", 0xB3DC, FP128, FP64>;
47 def CDGTR : UnaryRRE<"cdgtr", 0xB3F1, null_frag, FP64, GR64>;
50 def CDGTRA : TernaryRRFe<"cdgtra", 0xB3F1, FP64, GR64>;
52 def CDFTR : TernaryRRFe<"cdftr", 0xB951, FP64, GR32>;
59 def CDLGTR : TernaryRRFe<"cdlgtr", 0xB952, FP64, GR64>;
61 def CDLFTR : TernaryRRFe<"cdlftr", 0xB953, FP64, GR32>;
67 def CGDTR : BinaryRRFe<"cgdtr", 0xB3E1, GR64, FP64>;
[all …]
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| D | SystemZInstrFP.td | 22 def SelectF64 : SelectWrapper<f64, FP64>;
30 defm CondStoreF64 : CondStores<FP64, simple_store,
40 def LZDR : InherentRRE<"lzdr", 0xB375, FP64, fpimm0>;
46 def LDR : UnaryRR <"ldr", 0x28, null_frag, FP64, FP64>;
58 defm LTDBR : LoadAndTestRRE<"ltdbr", 0xB312, FP64>;
66 defm : CompareZeroFP<LTDBRCompare, FP64>;
75 def LTDBRCompare_VecPseudo : Pseudo<(outs), (ins FP64:$R1, FP64:$R2), []>;
80 defm : CompareZeroFP<LTDBRCompare_VecPseudo, FP64>;
86 def LGDR : UnaryRRE<"lgdr", 0xB3CD, bitconvert, GR64, FP64>;
87 def LDGR : UnaryRRE<"ldgr", 0xB3C1, bitconvert, FP64, GR64>;
[all …]
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| D | SystemZRegisterInfo.td | 218 defm FP64 : SystemZRegClass<"FP64", [f64], 64, (sequence "F%uD", 0, 15)>;
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| D | SystemZInstrVector.td | 1578 defm : ScalarToVectorFP<VREPG, v2f64, FP64, subreg_h64>;
1584 def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 0),
1585 (VPDI (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt,
1587 def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 1),
1588 (VPDI VR128:$vec, (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyRegisterInfo.td | 31 def FP64 : WebAssemblyReg<"%FP64">;
62 def I64 : WebAssemblyRegClass<[i64], 64, (add FP64, SP64, I64_0)>;
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| D | WebAssemblyRegisterInfo.cpp | 48 WebAssembly::FP64}) in getReservedRegs()
138 /* hasFP */ {WebAssembly::FP32, WebAssembly::FP64}}; in getFrameRegister()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.h | 117 bool FP64) const;
120 bool FP64) const;
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| D | MipsSEFrameLowering.cpp | 85 MachineBasicBlock::iterator I, bool FP64) const;
87 MachineBasicBlock::iterator I, bool FP64) const;
288 bool FP64) const { in expandBuildPairF64()
319 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in expandBuildPairF64()
344 bool FP64) const { in expandExtractElementF64()
384 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in expandExtractElementF64()
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| D | MipsSEInstrInfo.cpp | 770 bool FP64) const { in expandExtractElementF64()
802 get(isMicroMips ? (FP64 ? Mips::MFHC1_D64_MM : Mips::MFHC1_D32_MM) in expandExtractElementF64()
803 : (FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32)), in expandExtractElementF64()
812 bool isMicroMips, bool FP64) const { in expandBuildPairF64()
858 get(isMicroMips ? (FP64 ? Mips::MTHC1_D64_MM : Mips::MTHC1_D32_MM) in expandBuildPairF64()
859 : (FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32)), in expandBuildPairF64()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUSubtarget.h | 319 bool FP64; variable
480 return FP64; in hasFP64()
488 return FP64; in hasHWFP64()
1229 bool FP64; variable
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| D | AMDGPUFeatures.td | 10 "FP64",
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| D | AMDGPUSubtarget.cpp | 221 FP64(false), in GCNSubtarget()
542 FP64(false), in R600Subtarget()
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| /third_party/vk-gl-cts/external/vulkancts/modules/vulkan/spirv_assembly/ |
| D | vktSpvAsmFloatControlsTests.cpp | 56 FP64 enumerator
1323 m_floatType = FP64; in TypeTestResults()
1699 …mo[OID_CONV_FROM_FP64] = Op("conv_from_fp64", FLOAT_STORAGE_ONLY, false, FP64, "", convertSource, … in init()
1711 = Op("sconst_conv_from_fp64", FLOAT_ARITHMETIC, true, FP64, in init()
1717 = Op("sconst_conv_from_fp64", FLOAT_ARITHMETIC, true, FP64, in init()
2232 bool isFP64 = typeTestResults->floatType() == FP64; in build()
2904 m_typeData[FP64] = TypeData(); in TestGroupBuilderBase()
2905 m_typeData[FP64].values = TypeValuesSP(new TypeValues<double>); in TestGroupBuilderBase()
2906 m_typeData[FP64].snippets = TypeSnippetsSP(new TypeSnippets<double>); in TestGroupBuilderBase()
2907 m_typeData[FP64].testResults = TypeTestResultsSP(new TypeTestResults<double>); in TestGroupBuilderBase()
[all …]
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| /third_party/mesa3d/docs/relnotes/ |
| D | 12.0.4.rst | 193 - radeonsi: fix FP64 UBO loads with indirect uniform block indexing
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| D | 19.2.0.rst | 108 combination with FP64 on Intel.
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| D | 17.0.0.rst | 63 Add FP64 support to the i965 shader backends
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| D | 20.0.0.rst | 2770 - radv: enable FP16/FP64 denormals earlier and only for LLVM
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| D | 20.3.0.rst | 3431 - st/mesa: don't enable NV_copy_depth_to_color if NIR doesn't support FP64
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| /third_party/eudev/hwdb/ |
| D | 20-pci-vendor-model.hwdb | 40908 ID_MODEL_FROM_DATABASE=FDDI Adapter (FDDI SK-5841 (SK-NET FDDI-FP64))
|