| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 2144 // Match all load 128 bits width whose type is compatible with FPR128
2290 // Match all load 128 bits width whose type is compatible with FPR128
2474 // Match all load 128 bits width whose type is compatible with FPR128
2750 def : Pat<(store (f128 FPR128:$Rt),
2753 (STRQroW FPR128:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend128:$extend)>;
2754 def : Pat<(store (f128 FPR128:$Rt),
2757 (STRQroX FPR128:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Wextend128:$extend)>;
2806 // Match all store 128 bits width whose type is compatible with FPR128
2809 defm : VecROStorePat<ro128, v2i64, FPR128, STRQroW, STRQroX>;
2810 defm : VecROStorePat<ro128, v2f64, FPR128, STRQroW, STRQroX>;
[all …]
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| D | AArch64RegisterInfo.td | 435 def FPR128 : RegisterClass<"AArch64",
444 128, (trunc FPR128, 16)>;
465 def QSeqPairs : RegisterTuples<[qsub0, qsub1], [(rotl FPR128, 0), (rotl FPR128, 1)]>;
467 [(rotl FPR128, 0), (rotl FPR128, 1),
468 (rotl FPR128, 2)]>;
470 [(rotl FPR128, 0), (rotl FPR128, 1),
471 (rotl FPR128, 2), (rotl FPR128, 3)]>;
498 def V128 : RegisterOperand<FPR128, "printVRegOperand"> {
624 defm VecListOne : VectorList<1, FPR64, FPR128>;
652 def FPR128Op : RegisterOperand<FPR128, "printOperand"> {
[all …]
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| D | AArch64FrameLowering.cpp | 1910 enum RegType { GPR, FPR64, FPR128, PPR, ZPR } Type; enumerator
1924 case FPR128: in getScale()
1972 RPI.Type = RegPairInfo::FPR128; in computeCalleeSaveRegisterPairs()
1995 case RegPairInfo::FPR128: in computeCalleeSaveRegisterPairs()
2056 !RPI.isScalable() && RPI.Type != RegPairInfo::FPR128 && in computeCalleeSaveRegisterPairs()
2157 case RegPairInfo::FPR128: in spillCalleeSavedRegisters()
2263 case RegPairInfo::FPR128: in restoreCalleeSavedRegisters()
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| D | AArch64InstrFormats.td | 10433 : SHA3OpTiedInst<opc, asm, "", (outs FPR128:$dst),
10434 (ins FPR128:$Rd, FPR32:$Rn, V128:$Rm),
10435 [(set (v4i32 FPR128:$dst),
10436 (OpNode (v4i32 FPR128:$Rd), (i32 FPR32:$Rn),
10447 : SHA3OpTiedInst<opc, asm, "", (outs FPR128:$dst),
10448 (ins FPR128:$Rd, FPR128:$Rn, V128:$Rm),
10449 [(set (v4i32 FPR128:$dst),
10450 (OpNode (v4i32 FPR128:$Rd), (v4i32 FPR128:$Rn),
10529 : CryptoRRR<op0, op1, (outs FPR128:$Vdst), (ins FPR128:$Vd, FPR128:$Vn, V128:$Vm),
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenGlobalISel.inc | 1377 … } FPR128:{ *:[v2i64] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn,…
1402 … } FPR128:{ *:[v2i64] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn,…
7009 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38,
7010 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC FPR128*/38,
7030 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38,
7031 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC FPR128*/38,
7051 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, /*RC FPR128*/38,
7052 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, /*RC FPR128*/38,
7062 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38,
7063 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38,
[all …]
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| D | AArch64GenRegisterInfo.inc | 2658 // FPR128 Register Class...
2659 const MCPhysReg FPR128[] = {
2663 // FPR128 Bit set.
3475 { FPR128, FPR128Bits, 258, 32, sizeof(FPR128Bits), AArch64::FPR128RegClassID, 1, true },
5339 { 128, 128, 128, VTLists+17 }, // FPR128
12985 { // FPR128
12986 39, // bsub -> FPR128
12987 39, // dsub -> FPR128
12992 39, // hsub -> FPR128
12999 39, // ssub -> FPR128
[all …]
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| D | AArch64GenInstrInfo.inc | 18987 FPR128 = 392,
25323 OpTypes::FPR128, OpTypes::FPR128, OpTypes::FPR128, OpTypes::ccode,
27663 OpTypes::FPR128, OpTypes::FPR128, OpTypes::FPR32, OpTypes::V128,
27665 OpTypes::FPR128, OpTypes::FPR128, OpTypes::FPR32, OpTypes::V128,
27666 OpTypes::FPR128, OpTypes::FPR128, OpTypes::FPR32, OpTypes::V128,
27669 OpTypes::FPR128, OpTypes::FPR128, OpTypes::FPR128, OpTypes::V128,
27670 OpTypes::FPR128, OpTypes::FPR128, OpTypes::FPR128, OpTypes::V128,
27673 OpTypes::FPR128, OpTypes::FPR128, OpTypes::FPR128, OpTypes::V128,
27674 OpTypes::FPR128, OpTypes::FPR128, OpTypes::FPR128, OpTypes::V128,
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| D | AArch64GenAsmMatcher.inc | 7490 MCK_FPR128, // register class 'FPR128'
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.td | 191 class FPR128<bits<16> num, string n, FPR64 low, FPR64 high>
211 def F#I#Q : FPR128<I, "f"#I, !cast<FPR64>("F"#!add(I, 2)#"D"),
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