Searched refs:FinalReg (Results 1 – 3 of 3) sorted by relevance
1347 unsigned FinalReg = FinalOp.Mem.BaseReg; in VerifyAndAdjustOperands() local1368 bool IsSI = IsSIReg(FinalReg); in VerifyAndAdjustOperands()1369 FinalReg = GetSIDIForRegClass(RegClassID, FinalReg, IsSI); in VerifyAndAdjustOperands()1371 if (FinalReg != OrigReg) { in VerifyAndAdjustOperands()1381 FinalOp.Mem.BaseReg = FinalReg; in VerifyAndAdjustOperands()
595 FinalReg = InProlog ? X86::RDX in emitStackProbeInline() local656 BuildMI(&MBB, DL, TII.get(X86::CMOV64rr), FinalReg) in emitStackProbeInline()674 BuildMI(&MBB, DL, TII.get(X86::CMP64rr)).addReg(FinalReg).addReg(LimitReg); in emitStackProbeInline()679 RoundMBB->addLiveIn(FinalReg); in emitStackProbeInline()681 .addReg(FinalReg) in emitStackProbeInline()
702 unsigned FinalReg = SubReg; in buildSpillLoadStore() local729 FinalReg) in buildSpillLoadStore()