Searched refs:INTEL_L3P_RO (Results 1 – 6 of 6) sorted by relevance
75 const bool has_is = cfg->n[INTEL_L3P_IS] || cfg->n[INTEL_L3P_RO] || in setup_l3_config()77 const bool has_c = cfg->n[INTEL_L3P_C] || cfg->n[INTEL_L3P_RO] || in setup_l3_config()79 const bool has_t = cfg->n[INTEL_L3P_T] || cfg->n[INTEL_L3P_RO] || in setup_l3_config()125 SET_FIELD(cfg->n[INTEL_L3P_RO], GFX8_L3CNTLREG_RO_ALLOC) | in setup_l3_config()165 SET_FIELD(cfg->n[INTEL_L3P_RO], GFX7_L3CNTLREG2_RO_ALLOC) | in setup_l3_config()
272 w.w[INTEL_L3P_RO] = devinfo->is_baytrail ? 0.5 : 1.0; in intel_get_default_l3_weights()379 cfg->n[INTEL_L3P_DC], cfg->n[INTEL_L3P_RO], in intel_dump_l3_config()
44 INTEL_L3P_RO, enumerator
394 l3cr.ROAllocation = cfg->n[INTEL_L3P_RO]; in genX()403 const bool has_is = cfg->n[INTEL_L3P_IS] || cfg->n[INTEL_L3P_RO] || in genX()405 const bool has_c = cfg->n[INTEL_L3P_C] || cfg->n[INTEL_L3P_RO] || in genX()407 const bool has_t = cfg->n[INTEL_L3P_T] || cfg->n[INTEL_L3P_RO] || in genX()445 l3cr2.ROAllocation = cfg->n[INTEL_L3P_RO]; in genX()
1068 const bool has_is = cfg->n[INTEL_L3P_IS] || cfg->n[INTEL_L3P_RO] || in setup_l3_config()1070 const bool has_c = cfg->n[INTEL_L3P_C] || cfg->n[INTEL_L3P_RO] || in setup_l3_config()1072 const bool has_t = cfg->n[INTEL_L3P_T] || cfg->n[INTEL_L3P_RO] || in setup_l3_config()1117 reg.ROAllocation = cfg->n[INTEL_L3P_RO]; in setup_l3_config()1159 reg.ROAllocation = cfg->n[INTEL_L3P_RO]; in setup_l3_config()
772 reg.ROAllocation = cfg->n[INTEL_L3P_RO]; in iris_emit_l3_config()