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Searched refs:IR3_REG_SSA (Results 1 – 15 of 15) sorted by relevance

/third_party/mesa3d/src/freedreno/ir3/
Dir3_merge_regs.c370 if (!(pcopy->srcs[i]->flags & IR3_REG_SSA)) in aggressive_coalesce_parallel_copy()
390 if (!(collect->srcs[i]->flags & IR3_REG_SSA)) in aggressive_coalesce_collect()
413 if ((phi->srcs[pred_idx]->flags & IR3_REG_SSA) && in create_parallel_copy()
433 if ((phi->srcs[pred_idx]->flags & IR3_REG_SSA) && in create_parallel_copy()
459 if ((phi->srcs[pred_idx]->flags & IR3_REG_SSA) && in create_parallel_copy()
Dir3_array_to_ssa.c126 src_reg = ir3_src_create(phi, INVALID_REG, flags | IR3_REG_SSA); in read_value_beginning()
293 reg->flags |= IR3_REG_SSA; in ir3_array_to_ssa()
306 reg->flags |= IR3_REG_SSA; in ir3_array_to_ssa()
Dir3_ra.h98 return (reg->flags & IR3_REG_SSA) && reg->def && def_is_gpr(reg->def); in ra_reg_is_src()
104 return (reg->flags & IR3_REG_SSA) && def_is_gpr(reg) && in ra_reg_is_dst()
Dir3_cse.c133 if ((src->flags & IR3_REG_SSA) && src->def && in ir3_cse()
Dir3_context.c521 cond->dsts[0]->flags &= ~IR3_REG_SSA; in ir3_get_predicate()
654 IR3_REG_SSA | IR3_REG_ARRAY | flags | COND(address, IR3_REG_RELATIV)); in ir3_create_array_store()
660 ir3_src_create(mov, 0, IR3_REG_SSA | flags)->def = src->dsts[0]; in ir3_create_array_store()
Dir3_validate.c78 if (!(reg->flags & IR3_REG_SSA) || !reg->def) in validate_src()
152 if (reg->flags & IR3_REG_SSA) in validate_dst()
Dir3_print.c263 if (reg->flags & IR3_REG_SSA) { in print_reg_name()
274 } else if (reg->flags & IR3_REG_SSA) { in print_reg_name()
Dir3_cp.c137 *dstflags &= ~IR3_REG_SSA; in combine_flags()
138 *dstflags |= srcflags & IR3_REG_SSA; in combine_flags()
Dir3_ra.c1331 entry->interval->interval.reg->flags & ~IR3_REG_SSA); in insert_parallel_copy_instr()
1341 entry->interval->interval.reg->flags & ~IR3_REG_SSA); in insert_parallel_copy_instr()
1778 ir3_dst_create(pcopy, INVALID_REG, reg->flags & ~IR3_REG_SSA); in insert_liveout_copy()
1788 ir3_src_create(pcopy, INVALID_REG, reg->flags & ~IR3_REG_SSA); in insert_liveout_copy()
2296 instr->dsts[i]->flags &= ~IR3_REG_SSA; in ir3_ra()
2309 instr->srcs[i]->flags &= ~IR3_REG_SSA; in ir3_ra()
Dir3.h132 IR3_REG_SSA = 0x4000, /* 'def' is ptr to assigning destination */ enumerator
1166 if ((reg->flags & (IR3_REG_SSA | IR3_REG_ARRAY)) && reg->def) in ssa()
1709 reg = ir3_src_create(instr, INVALID_REG, IR3_REG_SSA | flags); in __ssa_src()
1718 struct ir3_register *reg = ir3_dst_create(instr, INVALID_REG, IR3_REG_SSA); in __ssa_dst()
Dir3_spill.c678 IR3_REG_CONST | IR3_REG_SSA | in spill()
1382 assert(new_val->flags & IR3_REG_SSA); in live_in_rewrite()
1666 if (!(interval->dst.flags & IR3_REG_SSA) || in record_live_out()
Dir3.c816 if (instr->srcs[n]->flags & IR3_REG_SSA) { in ir3_valid_flags()
Dir3_sched.c1044 if (!(instr->dsts[0]->flags & IR3_REG_SSA)) in is_output_only()
Dir3_compiler_nir.c2040 cond->dsts[0]->flags &= ~IR3_REG_SSA; in emit_intrinsic()
3205 cond->dsts[0]->flags &= ~IR3_REG_SSA; in emit_stream_out()
/third_party/mesa3d/docs/drivers/freedreno/
Dir3-notes.rst44 …s. And additionally, for normal (non-const, etc) src registers, the ``IR3_REG_SSA`` flag is set a…
113 If ``IR3_REG_SSA`` is set on a src register, the actual register