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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DTargetRegisterInfo.h579 LaneBitmask composeSubRegIndexLaneMask(unsigned IdxA, in composeSubRegIndexLaneMask() argument
581 if (!IdxA) in composeSubRegIndexLaneMask()
583 return composeSubRegIndexLaneMaskImpl(IdxA, Mask); in composeSubRegIndexLaneMask()
593 LaneBitmask reverseComposeSubRegIndexLaneMask(unsigned IdxA, in reverseComposeSubRegIndexLaneMask() argument
595 if (!IdxA) in reverseComposeSubRegIndexLaneMask()
597 return reverseComposeSubRegIndexLaneMaskImpl(IdxA, LaneMask); in reverseComposeSubRegIndexLaneMask()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenRegisterInfo.inc6156 unsigned MipsGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
6165 --IdxA; assert(IdxA < 11);
6167 return Rows[RowMap[IdxA]][IdxB];
6197 LaneBitmask MipsGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask…
6198 --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
6200 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
6210 LaneBitmask MipsGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask …
6211 LaneMask &= getSubRegIndexLaneMask(IdxA);
6212 --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
6214 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
DPPCGenRegisterInfo.inc5164 unsigned PPCGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
5169 --IdxA; assert(IdxA < 6);
5195 LaneBitmask PPCGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask)…
5196 --IdxA; assert(IdxA < 6 && "Subregister index out of bounds");
5198 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
5208 LaneBitmask PPCGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask L…
5209 LaneMask &= getSubRegIndexLaneMask(IdxA);
5210 --IdxA; assert(IdxA < 6 && "Subregister index out of bounds");
5212 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenRegisterInfo.inc8113 unsigned X86GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
8118 --IdxA; assert(IdxA < 10);
8149 LaneBitmask X86GenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask)…
8150 --IdxA; assert(IdxA < 10 && "Subregister index out of bounds");
8152 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
8162 LaneBitmask X86GenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask L…
8163 LaneMask &= getSubRegIndexLaneMask(IdxA);
8164 --IdxA; assert(IdxA < 10 && "Subregister index out of bounds");
8166 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenRegisterInfo.inc8435 unsigned ARMGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
8450 --IdxA; assert(IdxA < 56);
8452 return Rows[RowMap[IdxA]][IdxB];
8538 LaneBitmask ARMGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask)…
8539 --IdxA; assert(IdxA < 56 && "Subregister index out of bounds");
8541 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
8551 LaneBitmask ARMGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask L…
8552 LaneMask &= getSubRegIndexLaneMask(IdxA);
8553 --IdxA; assert(IdxA < 56 && "Subregister index out of bounds");
8555 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenRegisterInfo.inc8935 unsigned AArch64GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
8954 --IdxA; assert(IdxA < 99);
8956 return Rows[RowMap[IdxA]][IdxB];
9118 LaneBitmask AArch64GenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneM…
9119 --IdxA; assert(IdxA < 99 && "Subregister index out of bounds");
9121 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
9131 LaneBitmask AArch64GenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitma…
9132 LaneMask &= getSubRegIndexLaneMask(IdxA);
9133 --IdxA; assert(IdxA < 99 && "Subregister index out of bounds");
9135 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {