| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | PatternMatch.h | 1722 IntrinsicID_match(Intrinsic::ID IntrID) : ID(IntrID) {} in IntrinsicID_match()
1769 template <Intrinsic::ID IntrID> inline IntrinsicID_match m_Intrinsic() {
1770 return IntrinsicID_match(IntrID);
1773 template <Intrinsic::ID IntrID, typename T0>
1775 return m_CombineAnd(m_Intrinsic<IntrID>(), m_Argument<0>(Op0));
1778 template <Intrinsic::ID IntrID, typename T0, typename T1>
1781 return m_CombineAnd(m_Intrinsic<IntrID>(Op0), m_Argument<1>(Op1));
1784 template <Intrinsic::ID IntrID, typename T0, typename T1, typename T2>
1787 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1), m_Argument<2>(Op2));
1790 template <Intrinsic::ID IntrID, typename T0, typename T1, typename T2,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUPromoteAlloca.cpp | 273 Intrinsic::ID IntrID = Intrinsic::not_intrinsic; in getWorkitemID() local
277 IntrID = IsAMDGCN ? (Intrinsic::ID)Intrinsic::amdgcn_workitem_id_x in getWorkitemID()
281 IntrID = IsAMDGCN ? (Intrinsic::ID)Intrinsic::amdgcn_workitem_id_y in getWorkitemID()
286 IntrID = IsAMDGCN ? (Intrinsic::ID)Intrinsic::amdgcn_workitem_id_z in getWorkitemID()
293 Function *WorkitemIdFn = Intrinsic::getDeclaration(Mod, IntrID); in getWorkitemID()
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| D | AMDGPUISelDAGToDAG.cpp | 302 void SelectDSAppendConsume(SDNode *N, unsigned IntrID);
303 void SelectDS_GWS(SDNode *N, unsigned IntrID);
2213 void AMDGPUDAGToDAGISel::SelectDSAppendConsume(SDNode *N, unsigned IntrID) { in SelectDSAppendConsume() argument
2216 unsigned Opc = IntrID == Intrinsic::amdgcn_ds_append ? in SelectDSAppendConsume()
2253 static unsigned gwsIntrinToOpcode(unsigned IntrID) { in gwsIntrinToOpcode() argument
2254 switch (IntrID) { in gwsIntrinToOpcode()
2272 void AMDGPUDAGToDAGISel::SelectDS_GWS(SDNode *N, unsigned IntrID) { in SelectDS_GWS() argument
2273 if (IntrID == Intrinsic::amdgcn_ds_gws_sema_release_all && in SelectDS_GWS()
2329 const unsigned Opc = gwsIntrinToOpcode(IntrID); in SelectDS_GWS()
2342 unsigned IntrID = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); in SelectINTRINSIC_W_CHAIN() local
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| D | AMDGPUCodeGenPrepare.cpp | 480 Intrinsic::ID IntrID = Intrinsic::not_intrinsic; in replaceMulWithMul24() local
484 IntrID = Intrinsic::amdgcn_mul_u24; in replaceMulWithMul24()
486 IntrID = Intrinsic::amdgcn_mul_i24; in replaceMulWithMul24()
498 FunctionCallee Intrin = Intrinsic::getDeclaration(Mod, IntrID); in replaceMulWithMul24()
501 if (IntrID == Intrinsic::amdgcn_mul_u24) { in replaceMulWithMul24()
511 if (IntrID == Intrinsic::amdgcn_mul_u24) { in replaceMulWithMul24()
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| D | AMDGPUTargetTransformInfo.cpp | 671 auto IntrID = II->getIntrinsicID(); in rewriteIntrinsicWithAddressSpace() local
672 switch (IntrID) { in rewriteIntrinsicWithAddressSpace()
692 unsigned TrueAS = IntrID == Intrinsic::amdgcn_is_shared ? in rewriteIntrinsicWithAddressSpace()
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| D | AMDGPURegisterBankInfo.cpp | 2141 auto IntrID = MI.getIntrinsicID(); in applyMappingImpl() local
2142 switch (IntrID) { in applyMappingImpl()
2196 AMDGPU::lookupRsrcIntrinsic(IntrID)) { in applyMappingImpl()
3093 auto IntrID = MI.getIntrinsicID(); in getInstrMapping() local
3094 switch (IntrID) { in getInstrMapping()
3255 AMDGPU::lookupRsrcIntrinsic(IntrID)) { in getInstrMapping()
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| D | SIISelLowering.cpp | 924 unsigned IntrID) const { in getTgtMemIntrinsic()
926 AMDGPU::lookupRsrcIntrinsic(IntrID)) { in getTgtMemIntrinsic()
928 (Intrinsic::ID)IntrID); in getTgtMemIntrinsic()
973 switch (IntrID) { in getTgtMemIntrinsic()
1052 if (IntrID == Intrinsic::amdgcn_ds_gws_barrier) in getTgtMemIntrinsic()
6136 unsigned IntrID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); in LowerINTRINSIC_W_CHAIN() local
6139 switch (IntrID) { in LowerINTRINSIC_W_CHAIN()
6169 switch (IntrID) { in LowerINTRINSIC_W_CHAIN()
6221 switch (IntrID) { in LowerINTRINSIC_W_CHAIN()
6237 switch (IntrID) { in LowerINTRINSIC_W_CHAIN()
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| D | AMDGPULegalizerInfo.cpp | 2352 auto IntrID = MI.getIntrinsicID(); in legalizeIntrinsic() local
2353 switch (IntrID) { in legalizeIntrinsic()
2369 if (IntrID == Intrinsic::amdgcn_if) { in legalizeIntrinsic()
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| D | AMDGPUInstructionSelector.cpp | 1048 MachineInstr &MI, Intrinsic::ID IntrID) const { in selectDSOrderedIntrinsic()
1077 unsigned Instruction = IntrID == Intrinsic::amdgcn_ds_ordered_add ? 0 : 1; in selectDSOrderedIntrinsic()
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| D | AMDGPUISelLowering.cpp | 715 unsigned IntrID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); in isSDNodeAlwaysUniform() local
716 switch (IntrID) { in isSDNodeAlwaysUniform()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | MachineVerifier.cpp | 1355 unsigned IntrID = IntrIDOp.getIntrinsicID(); in verifyPreISelGenericInstruction() local
1356 if (IntrID != 0 && IntrID < Intrinsic::num_intrinsics) { in verifyPreISelGenericInstruction()
1359 static_cast<Intrinsic::ID>(IntrID)); in verifyPreISelGenericInstruction()
1370 switch (IntrID) { in verifyPreISelGenericInstruction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Utils/ |
| D | AMDGPUBaseInfo.h | 664 bool isIntrinsicSourceOfDivergence(unsigned IntrID);
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| D | AMDGPUBaseInfo.cpp | 1339 bool isIntrinsicSourceOfDivergence(unsigned IntrID) { in isIntrinsicSourceOfDivergence() argument
1340 return lookupSourceOfDivergence(IntrID); in isIntrinsicSourceOfDivergence()
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