| /third_party/libsnd/src/GSM610/ |
| D | lpc.c | 281 register int16_t * LAR /* [0..7] IN/OUT */ in Quantization_and_coding() argument
297 temp = GSM_MULT (A, *LAR) ; \ in Quantization_and_coding()
301 *LAR = temp > MAC ? MAC - MIC : (temp < MIC ? 0 : temp - MIC) ; \ in Quantization_and_coding()
302 LAR++ ; in Quantization_and_coding()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Transforms/Scalar/ |
| D | LoopPassManager.h | 301 LoopStandardAnalysisResults LAR = {AM.getResult<AAManager>(F),
348 assert(L->isRecursivelyLCSSAForm(LAR.DT, LI) &&
356 PreservedAnalyses PassPA = Pass.run(*L, LAM, LAR, Updater);
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Vectorize/ |
| D | LoopVectorizationLegality.cpp | 841 const OptimizationRemarkAnalysis *LAR = LAI->getReport(); in canVectorizeMemory() local
842 if (LAR) { in canVectorizeMemory()
845 "loop not vectorized: ", *LAR); in canVectorizeMemory()
|
| /third_party/cmsis/CMSIS/Core/Include/ |
| D | core_cm7.h | 1056 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ member
1154 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ member
|
| D | core_armv8mml.h | 1030 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ member
1313 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ member
|
| D | core_sc300.h | 759 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ member
|
| D | core_cm3.h | 774 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ member
|
| D | core_armv81mml.h | 1091 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ member
1375 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ member
|
| D | core_cm55.h | 1091 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ member
1409 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ member
|
| D | core_cm4.h | 832 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ member
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| D | core_armv8mbl.h | 740 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ member
|
| D | core_cm33.h | 1030 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ member
|
| D | core_cm35p.h | 1030 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ member
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/ |
| D | ScalarEvolution.cpp | 9940 const auto *LAR = cast<SCEVAddRecExpr>(Less); in computeConstantDifference() local
9943 if (LAR->getLoop() != MAR->getLoop()) in computeConstantDifference()
9948 if (!LAR->isAffine() || !MAR->isAffine()) in computeConstantDifference()
9951 if (LAR->getStepRecurrence(*this) != MAR->getStepRecurrence(*this)) in computeConstantDifference()
9954 Less = LAR->getStart(); in computeConstantDifference()
10215 const SCEVAddRecExpr *LAR = dyn_cast<SCEVAddRecExpr>(LHS); in IsKnownPredicateViaAddRecStart() local
10216 if (!LAR) in IsKnownPredicateViaAddRecStart()
10221 if (LAR->getLoop() != RAR->getLoop()) in IsKnownPredicateViaAddRecStart()
10223 if (!LAR->isAffine() || !RAR->isAffine()) in IsKnownPredicateViaAddRecStart()
10226 if (LAR->getStepRecurrence(SE) != RAR->getStepRecurrence(SE)) in IsKnownPredicateViaAddRecStart()
[all …]
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86SchedBroadwell.td | 1250 def: InstRW<[BWWriteResGroup113], (instregex "LAR(16|32|64)rm",
1345 def: InstRW<[BWWriteResGroup144], (instregex "LAR(16|32|64)rr")>;
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| D | X86SchedHaswell.td | 1433 def: InstRW<[HWWriteResGroup83], (instregex "LAR(16|32|64)rr")>;
1440 def: InstRW<[HWWriteResGroup87], (instregex "LAR(16|32|64)rm",
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| D | X86SchedSkylakeClient.td | 901 def: InstRW<[SKLWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
1308 def: InstRW<[SKLWriteResGroup131], (instregex "LAR(16|32|64)rm",
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| D | X86SchedSkylakeServer.td | 1013 def: InstRW<[SKXWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
1735 def: InstRW<[SKXWriteResGroup146], (instregex "LAR(16|32|64)rm",
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| D | X86ScheduleBdVer2.td | 313 def : InstRW<[PdWriteLARrr], (instregex "LAR(16|32|64)rr",
|
| /third_party/mesa3d/src/mesa/x86/ |
| D | assyntax.h | 502 #define LAR(a, b) CHOICE(lar ARG2(a, b), lar ARG2(a, b), lar ARG2(b, a)) macro
1220 #define LAR(a, b) lar b, a macro
|