Searched refs:LoOpc (Results 1 – 6 of 6) sorted by relevance
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
D | MipsSEInstrInfo.h | 99 unsigned LoOpc, unsigned HiOpc,
|
D | MipsSEInstrInfo.cpp | 715 unsigned LoOpc, in expandPseudoMTLoHi() argument 726 MachineInstrBuilder LoInst = BuildMI(MBB, I, DL, get(LoOpc)); in expandPseudoMTLoHi()
|
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
D | HexagonCopyToCombine.cpp | 187 unsigned LoOpc = LowRegInst.getOpcode(); in areCombinableOperations() local 200 verifyOpc(LoOpc); in areCombinableOperations() 202 if (HiOpc == Hexagon::V6_vassign || LoOpc == Hexagon::V6_vassign) in areCombinableOperations() 203 return HiOpc == LoOpc; in areCombinableOperations()
|
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
D | LegalizeIntegerTypes.cpp | 2222 ISD::NodeType LoOpc; in ExpandIntRes_MINMAX() local 2224 std::tie(CondC, LoOpc) = getExpandedMinMaxOps(N->getOpcode()); in ExpandIntRes_MINMAX() 2247 SDValue LoMinMax = DAG.getNode(LoOpc, DL, NVT, {LHSL, RHSL}); in ExpandIntRes_MINMAX()
|
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | SIInstrInfo.cpp | 5387 unsigned LoOpc = IsAdd ? AMDGPU::V_ADD_I32_e64 : AMDGPU::V_SUB_I32_e64; in splitScalar64BitAddSub() local 5389 BuildMI(MBB, MII, DL, get(LoOpc), DestSub0) in splitScalar64BitAddSub()
|
D | SIISelLowering.cpp | 3635 unsigned LoOpc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32; in EmitInstrWithCustomInserter() local 3637 BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0) in EmitInstrWithCustomInserter()
|