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Searched refs:MAX_SETS (Results 1 – 25 of 33) sorted by relevance

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/third_party/mesa3d/src/freedreno/vulkan/
Dtu_descriptor_set.h32 #define MAX_SETS 4 macro
104 } set[MAX_SETS];
Dtu_shader.c209 set = MAX_SETS; in lower_vulkan_resource_index()
271 nir_ssa_def *results[MAX_SETS + 1] = { NULL }; in lower_ssbo_ubo_intrinsic()
281 for (unsigned i = 0; i < MAX_SETS + 1; i++) { in lower_ssbo_ubo_intrinsic()
320 for (int i = MAX_SETS; i >= 0; i--) { in lower_ssbo_ubo_intrinsic()
Dtu_cmd_buffer.c1804 uint64_t addr[MAX_SETS + 1] = {}; in tu_CmdBindDescriptorSets()
1807 for (uint32_t i = 0; i < MAX_SETS; i++) { in tu_CmdBindDescriptorSets()
1825 addr[MAX_SETS] = dynamic_desc_set.iova | 3; in tu_CmdBindDescriptorSets()
3315 uint32_t *base = state->range[i].ubo.bindless_base == MAX_SETS ? in tu6_user_consts_size()
3390 uint32_t *base = state->range[i].ubo.bindless_base == MAX_SETS ? in tu6_emit_user_consts()
Dtu_private.h726 struct tu_descriptor_set *sets[MAX_SETS];
Dtu_descriptor_set.c1086 assert(pCreateInfo->set < MAX_SETS); in tu_CreateDescriptorUpdateTemplate()
Dtu_pipeline.c175 base = MAX_SETS; in tu6_emit_load_state()
208 base = MAX_SETS; in tu6_emit_load_state()
/third_party/mesa3d/src/broadcom/vulkan/
Dv3dv_limits.h38 #define MAX_SETS 16 macro
Dv3dv_private.h1089 struct v3dv_descriptor_set *descriptor_sets[MAX_SETS];
1587 } set[MAX_SETS];
/third_party/mesa3d/src/amd/vulkan/
Dradv_shader_args.h36 struct ac_arg descriptor_sets[MAX_SETS];
Dradv_constants.h78 #define MAX_SETS 32 macro
Dradv_descriptor_set.h95 } set[MAX_SETS];
Dradv_shader.h184 struct radv_userdata_info descriptor_sets[MAX_SETS];
Dradv_debug.c247 for (i = 0; i < MAX_SETS; i++) { in radv_dump_descriptors()
Dradv_shader_args.c523 for (int i = 0; i < MAX_SETS; i++) in radv_declare_shader_args()
Dradv_cmd_buffer.c766 uint32_t data[MAX_SETS * 2] = {0}; in radv_save_descriptors()
777 radv_emit_write_data_packet(cmd_buffer, V_370_ME, va, MAX_SETS * 2, data); in radv_save_descriptors()
3090 uint32_t size = MAX_SETS * 4; in radv_flush_indirect_descriptor_sets()
3097 for (unsigned i = 0; i < MAX_SETS; i++) { in radv_flush_indirect_descriptor_sets()
3155 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, MAX_SETS * MESA_SHADER_STAGES * 4); in radv_flush_descriptors()
Dradv_descriptor_set.c1333 assert(pCreateInfo->set < MAX_SETS); in radv_CreateDescriptorUpdateTemplate()
/third_party/mesa3d/src/panfrost/vulkan/
Dpanvk_descriptor_set.c244 if (tex_idx > PANVK_MAX_TEXTURES / MAX_SETS || in panvk_GetDescriptorSetLayoutSupport()
245 sampler_idx > PANVK_MAX_SAMPLERS / MAX_SETS || in panvk_GetDescriptorSetLayoutSupport()
246 ubo_idx > PANVK_MAX_UBOS / MAX_SETS) in panvk_GetDescriptorSetLayoutSupport()
Dpanvk_private.h357 #define MAX_SETS 4 macro
428 } sets[MAX_SETS];
482 } sets[MAX_SETS];
Dpanvk_device.c739 .maxBoundDescriptorSets = MAX_SETS, in panvk_GetPhysicalDeviceProperties2()
/third_party/mesa3d/src/gallium/frontends/lavapipe/
Dlvp_private.h75 #define MAX_SETS 8 macro
465 } set[MAX_SETS];
/third_party/mesa3d/src/intel/vulkan/
Danv_nir_compute_push_layout.c243 if (binding->set < MAX_SETS && robust_buffer_access) { in anv_nir_compute_push_layout()
Danv_private.h185 #define MAX_SETS 8 macro
2266 } set[MAX_SETS];
2710 uint64_t desc_sets[MAX_SETS];
2900 struct anv_descriptor_set *descriptors[MAX_SETS];
2901 struct anv_push_descriptor_set *push_descriptors[MAX_SETS];
Danv_cmd_buffer.c1016 assert(firstSet + descriptorSetCount <= MAX_SETS); in anv_CmdBindDescriptorSets()
1455 assert(_set < MAX_SETS); in anv_CmdPushDescriptorSetKHR()
Danv_nir_apply_pipeline_layout.c59 } set[MAX_SETS];
DgenX_cmd_buffer.c2689 assert(binding->set < MAX_SETS); in emit_binding_table()
3070 assert(range->set < MAX_SETS); in get_push_range_address()
3135 assert(range->set < MAX_SETS); in get_push_range_bound_size()

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