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Searched refs:MI (Results 1 – 25 of 958) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZShortenInst.cpp43 bool shortenIIF(MachineInstr &MI, unsigned LLIxL, unsigned LLIxH);
44 bool shortenOn0(MachineInstr &MI, unsigned Opcode);
45 bool shortenOn01(MachineInstr &MI, unsigned Opcode);
46 bool shortenOn001(MachineInstr &MI, unsigned Opcode);
47 bool shortenOn001AddCC(MachineInstr &MI, unsigned Opcode);
48 bool shortenFPConv(MachineInstr &MI, unsigned Opcode);
66 static void tieOpsIfNeeded(MachineInstr &MI) { in tieOpsIfNeeded() argument
67 if (MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) && in tieOpsIfNeeded()
68 !MI.getOperand(0).isTied()) in tieOpsIfNeeded()
69 MI.tieOperands(0, 1); in tieOpsIfNeeded()
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DSystemZAsmPrinter.cpp33 static MCInst lowerRILow(const MachineInstr *MI, unsigned Opcode) { in lowerRILow() argument
34 if (MI->isCompare()) in lowerRILow()
36 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
37 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
40 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
41 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
42 .addImm(MI->getOperand(2).getImm()); in lowerRILow()
47 static MCInst lowerRIHigh(const MachineInstr *MI, unsigned Opcode) { in lowerRIHigh() argument
48 if (MI->isCompare()) in lowerRIHigh()
50 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DExpandPostRAPseudos.cpp51 bool LowerSubregToReg(MachineInstr *MI);
52 bool LowerCopy(MachineInstr *MI);
54 void TransferImplicitOperands(MachineInstr *MI);
67 void ExpandPostRA::TransferImplicitOperands(MachineInstr *MI) { in TransferImplicitOperands() argument
68 MachineBasicBlock::iterator CopyMI = MI; in TransferImplicitOperands()
71 for (const MachineOperand &MO : MI->implicit_operands()) in TransferImplicitOperands()
76 bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) { in LowerSubregToReg() argument
77 MachineBasicBlock *MBB = MI->getParent(); in LowerSubregToReg()
78 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) && in LowerSubregToReg()
79 MI->getOperand(1).isImm() && in LowerSubregToReg()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.h57 unsigned isLoadFromStackSlot(const MachineInstr &MI,
65 unsigned isStoreToStackSlot(const MachineInstr &MI,
72 const MachineInstr &MI,
79 const MachineInstr &MI,
204 bool expandPostRAPseudo(MachineInstr &MI) const override;
219 MachineBasicBlock::iterator MI) const override;
222 bool isPredicated(const MachineInstr &MI) const override;
225 bool isPostIncrement(const MachineInstr &MI) const override;
229 bool PredicateInstruction(MachineInstr &MI,
240 bool DefinesPredicate(MachineInstr &MI,
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DHexagonInstrInfo.cpp185 static inline void parseOperands(const MachineInstr &MI, in parseOperands() argument
190 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { in parseOperands()
191 const MachineOperand &MO = MI.getOperand(i); in parseOperands()
239 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, in isLoadFromStackSlot() argument
241 switch (MI.getOpcode()) { in isLoadFromStackSlot()
254 const MachineOperand OpFI = MI.getOperand(1); in isLoadFromStackSlot()
257 const MachineOperand OpOff = MI.getOperand(2); in isLoadFromStackSlot()
261 return MI.getOperand(0).getReg(); in isLoadFromStackSlot()
268 const MachineOperand OpFI = MI.getOperand(2); in isLoadFromStackSlot()
271 const MachineOperand OpOff = MI.getOperand(3); in isLoadFromStackSlot()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DGCNHazardRecognizer.cpp57 void GCNHazardRecognizer::EmitInstruction(MachineInstr *MI) { in EmitInstruction() argument
58 CurrCycleInstr = MI; in EmitInstruction()
94 const MachineInstr &MI) { in isSendMsgTraceDataOrGDS() argument
95 if (TII.isAlwaysGDS(MI.getOpcode())) in isSendMsgTraceDataOrGDS()
98 switch (MI.getOpcode()) { in isSendMsgTraceDataOrGDS()
109 if (TII.isDS(MI.getOpcode())) { in isSendMsgTraceDataOrGDS()
110 int GDS = AMDGPU::getNamedOperandIdx(MI.getOpcode(), in isSendMsgTraceDataOrGDS()
112 if (MI.getOperand(GDS).getImm()) in isSendMsgTraceDataOrGDS()
119 static bool isPermlane(const MachineInstr &MI) { in isPermlane() argument
120 unsigned Opcode = MI.getOpcode(); in isPermlane()
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DSIInstrInfo.h69 unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
75 MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI,
135 unsigned findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const;
138 bool swapSourceModifiers(MachineInstr &MI,
142 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
177 bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
196 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
200 unsigned calculateLDSSpillAddress(MachineBasicBlock &MBB, MachineInstr &MI,
205 MachineBasicBlock::iterator MI,
222 MachineBasicBlock::iterator MI, unsigned SrcReg,
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DSIMemoryLegalizer.cpp104 bool enableNamedBit(const MachineBasicBlock::iterator &MI) { in enableNamedBit() argument
105 int BitIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), BitName); in enableNamedBit()
109 MachineOperand &Bit = MI->getOperand(BitIdx); in enableNamedBit()
207 void reportUnsupported(const MachineBasicBlock::iterator &MI,
223 const MachineBasicBlock::iterator &MI) const;
232 const MachineBasicBlock::iterator &MI) const;
236 const MachineBasicBlock::iterator &MI) const;
241 const MachineBasicBlock::iterator &MI) const;
246 const MachineBasicBlock::iterator &MI) const;
267 virtual bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86ATTInstPrinter.h27 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
29 bool printVecCompareInstr(const MCInst *MI, raw_ostream &OS);
33 bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
34 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
38 void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &OS);
41 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS) override;
42 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS);
43 void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
44 void printSrcIdx(const MCInst *MI, unsigned Op, raw_ostream &O);
45 void printDstIdx(const MCInst *MI, unsigned Op, raw_ostream &O);
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DX86IntelInstPrinter.h28 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
30 bool printVecCompareInstr(const MCInst *MI, raw_ostream &OS);
34 bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
35 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
39 void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
42 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) override;
43 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O);
44 void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O);
45 void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O);
46 void printDstIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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DX86InstComments.cpp215 static unsigned getRegOperandNumElts(const MCInst *MI, unsigned ScalarSize, in getRegOperandNumElts() argument
217 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandNumElts()
226 static void printMasking(raw_ostream &OS, const MCInst *MI, in printMasking() argument
228 const MCInstrDesc &Desc = MCII.get(MI->getOpcode()); in printMasking()
240 const char *MaskRegName = getRegName(MI->getOperand(MaskOp).getReg()); in printMasking()
250 static bool printFMA3Comments(const MCInst *MI, raw_ostream &OS) { in printFMA3Comments() argument
252 unsigned NumOperands = MI->getNumOperands(); in printFMA3Comments()
265 switch (MI->getOpcode()) { in printFMA3Comments()
270 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMA3Comments()
275 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); in printFMA3Comments()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/
DMipsInstPrinter.cpp31 static bool isReg(const MCInst &MI, unsigned OpNo) { in isReg() argument
32 assert(MI.getOperand(OpNo).isReg() && "Register operand expected."); in isReg()
33 return MI.getOperand(OpNo).getReg() == R; in isReg()
78 void MipsInstPrinter::printInst(const MCInst *MI, uint64_t Address, in printInst() argument
81 switch (MI->getOpcode()) { in printInst()
91 printSaveRestore(MI, O); in printInst()
96 printSaveRestore(MI, O); in printInst()
101 printSaveRestore(MI, O); in printInst()
106 printSaveRestore(MI, O); in printInst()
112 if (!printAliasInstr(MI, O) && !printAlias(*MI, O)) in printInst()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/MCTargetDesc/
DAMDGPUInstPrinter.h26 void printInstruction(const MCInst *MI, uint64_t Address,
30 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
36 void printU4ImmOperand(const MCInst *MI, unsigned OpNo,
38 void printU8ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
39 void printU16ImmOperand(const MCInst *MI, unsigned OpNo,
41 void printU4ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
42 void printU8ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
43 void printU16ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
44 void printU32ImmOperand(const MCInst *MI, unsigned OpNo,
46 void printNamedBit(const MCInst *MI, unsigned OpNo, raw_ostream &O,
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DAMDGPUInstPrinter.cpp29 void AMDGPUInstPrinter::printInst(const MCInst *MI, uint64_t Address, in printInst() argument
33 printInstruction(MI, Address, STI, OS); in printInst()
37 void AMDGPUInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo, in printU4ImmOperand() argument
40 O << formatHex(MI->getOperand(OpNo).getImm() & 0xf); in printU4ImmOperand()
43 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo, in printU8ImmOperand() argument
45 O << formatHex(MI->getOperand(OpNo).getImm() & 0xff); in printU8ImmOperand()
48 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo, in printU16ImmOperand() argument
53 int64_t Imm = MI->getOperand(OpNo).getImm(); in printU16ImmOperand()
57 printU32ImmOperand(MI, OpNo, STI, O); in printU16ImmOperand()
60 void AMDGPUInstPrinter::printU4ImmDecOperand(const MCInst *MI, unsigned OpNo, in printU4ImmDecOperand() argument
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/
DARMInstPrinter.h28 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
33 void printInstruction(const MCInst *MI, uint64_t Address,
35 virtual bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
37 virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
44 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
47 void printSORegRegOperand(const MCInst *MI, unsigned OpNum,
49 void printSORegImmOperand(const MCInst *MI, unsigned OpNum,
52 void printAddrModeTBB(const MCInst *MI, unsigned OpNum,
54 void printAddrModeTBH(const MCInst *MI, unsigned OpNum,
56 void printAddrMode2Operand(const MCInst *MI, unsigned OpNum,
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DARMInstPrinter.cpp91 void ARMInstPrinter::printInst(const MCInst *MI, uint64_t Address, in printInst() argument
94 unsigned Opcode = MI->getOpcode(); in printInst()
100 const MCOperand &Dst = MI->getOperand(0); in printInst()
101 const MCOperand &MO1 = MI->getOperand(1); in printInst()
102 const MCOperand &MO2 = MI->getOperand(2); in printInst()
103 const MCOperand &MO3 = MI->getOperand(3); in printInst()
106 printSBitModifierOperand(MI, 6, STI, O); in printInst()
107 printPredicateOperand(MI, 4, STI, O); in printInst()
123 const MCOperand &Dst = MI->getOperand(0); in printInst()
124 const MCOperand &MO1 = MI->getOperand(1); in printInst()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/MCTargetDesc/
DSystemZMCCodeEmitter.cpp47 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
53 uint64_t getBinaryCodeForInstr(const MCInst &MI,
59 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
67 uint64_t getBDAddr12Encoding(const MCInst &MI, unsigned OpNum,
70 uint64_t getBDAddr20Encoding(const MCInst &MI, unsigned OpNum,
73 uint64_t getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum,
76 uint64_t getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum,
79 uint64_t getBDLAddr12Len4Encoding(const MCInst &MI, unsigned OpNum,
82 uint64_t getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum,
85 uint64_t getBDRAddr12Encoding(const MCInst &MI, unsigned OpNum,
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DSystemZInstPrinter.cpp58 void SystemZInstPrinter::printInst(const MCInst *MI, uint64_t Address, in printInst() argument
61 printInstruction(MI, Address, O); in printInst()
70 static void printUImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) { in printUImmOperand() argument
71 int64_t Value = MI->getOperand(OpNum).getImm(); in printUImmOperand()
77 static void printSImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) { in printSImmOperand() argument
78 int64_t Value = MI->getOperand(OpNum).getImm(); in printSImmOperand()
83 void SystemZInstPrinter::printU1ImmOperand(const MCInst *MI, int OpNum, in printU1ImmOperand() argument
85 printUImmOperand<1>(MI, OpNum, O); in printU1ImmOperand()
88 void SystemZInstPrinter::printU2ImmOperand(const MCInst *MI, int OpNum, in printU2ImmOperand() argument
90 printUImmOperand<2>(MI, OpNum, O); in printU2ImmOperand()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/MCTargetDesc/
DPPCMCCodeEmitter.cpp43 getDirectBrEncoding(const MCInst &MI, unsigned OpNo, in getDirectBrEncoding() argument
46 const MCOperand &MO = MI.getOperand(OpNo); in getDirectBrEncoding()
47 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getDirectBrEncoding()
55 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo, in getCondBrEncoding() argument
58 const MCOperand &MO = MI.getOperand(OpNo); in getCondBrEncoding()
59 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getCondBrEncoding()
68 getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, in getAbsDirectBrEncoding() argument
71 const MCOperand &MO = MI.getOperand(OpNo); in getAbsDirectBrEncoding()
72 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsDirectBrEncoding()
81 getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, in getAbsCondBrEncoding() argument
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DPPCInstPrinter.cpp67 void PPCInstPrinter::printInst(const MCInst *MI, uint64_t Address, in printInst() argument
75 (MI->getOpcode() == PPC::ADDIS8 || MI->getOpcode() == PPC::ADDIS) && in printInst()
76 MI->getOperand(2).isExpr()) { in printInst()
77 assert((MI->getOperand(0).isReg() && MI->getOperand(1).isReg()) && in printInst()
81 assert(isa<MCSymbolRefExpr>(MI->getOperand(2).getExpr()) && in printInst()
86 printOperand(MI, 0, O); in printInst()
88 printOperand(MI, 2, O); in printInst()
90 printOperand(MI, 1, O); in printInst()
96 if (MI->getOpcode() == PPC::RLWINM) { in printInst()
97 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiInstPrinter.cpp38 bool LanaiInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, in printInst() argument
42 printOperand(MI, OpNo0, OS); in printInst()
44 printOperand(MI, OpNo1, OS); in printInst()
48 static bool usesGivenOffset(const MCInst *MI, int AddOffset) { in usesGivenOffset() argument
49 unsigned AluCode = MI->getOperand(3).getImm(); in usesGivenOffset()
51 (MI->getOperand(2).getImm() == AddOffset || in usesGivenOffset()
52 MI->getOperand(2).getImm() == -AddOffset); in usesGivenOffset()
55 static bool isPreIncrementForm(const MCInst *MI, int AddOffset) { in isPreIncrementForm() argument
56 unsigned AluCode = MI->getOperand(3).getImm(); in isPreIncrementForm()
57 return LPAC::isPreOp(AluCode) && usesGivenOffset(MI, AddOffset); in isPreIncrementForm()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/
DARCBranchFinalize.cpp51 void replaceWithBRcc(MachineInstr *MI) const;
52 void replaceWithCmpBcc(MachineInstr *MI) const;
95 static bool isBRccPseudo(MachineInstr *MI) { in isBRccPseudo() argument
96 return !(MI->getOpcode() != ARC::BRcc_rr_p && in isBRccPseudo()
97 MI->getOpcode() != ARC::BRcc_ru6_p); in isBRccPseudo()
100 static unsigned getBRccForPseudo(MachineInstr *MI) { in getBRccForPseudo() argument
101 assert(isBRccPseudo(MI) && "Can't get BRcc for wrong instruction."); in getBRccForPseudo()
102 if (MI->getOpcode() == ARC::BRcc_rr_p) in getBRccForPseudo()
107 static unsigned getCmpForPseudo(MachineInstr *MI) { in getCmpForPseudo() argument
108 assert(isBRccPseudo(MI) && "Can't get BRcc for wrong instruction."); in getCmpForPseudo()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DLegalizerHelper.h63 LegalizeResult legalizeInstrStep(MachineInstr &MI);
66 LegalizeResult libcall(MachineInstr &MI);
70 LegalizeResult narrowScalar(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy);
75 LegalizeResult widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
79 LegalizeResult lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
83 LegalizeResult fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
88 LegalizeResult moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
103 void widenScalarSrc(MachineInstr &MI, LLT WideTy, unsigned OpIdx,
109 void narrowScalarSrc(MachineInstr &MI, LLT NarrowTy, unsigned OpIdx);
114 void widenScalarDst(MachineInstr &MI, LLT WideTy, unsigned OpIdx = 0,
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64InstPrinter.h28 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
33 virtual void printInstruction(const MCInst *MI, uint64_t Address,
35 virtual bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
37 virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
50 bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI,
53 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
55 void printImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
57 void printImmHex(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
60 void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm,
63 void printPostIncOperand(const MCInst *MI, unsigned OpNo, in printPostIncOperand() argument
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DAArch64MCCodeEmitter.cpp56 uint64_t getBinaryCodeForInstr(const MCInst &MI,
62 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
70 uint32_t getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
76 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
82 uint32_t getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
88 uint32_t getCondBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
94 uint32_t getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
101 uint32_t getMemExtendOpValue(const MCInst &MI, unsigned OpIdx,
107 uint32_t getTestBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
113 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
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