| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 47 bool selectCmp(CmpConstants Helper, MachineInstrBuilder &MIB,
60 bool selectGlobal(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
61 bool selectSelect(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
62 bool selectShift(unsigned ShiftOpc, MachineInstrBuilder &MIB) const;
233 static bool selectMergeValues(MachineInstrBuilder &MIB, in selectMergeValues() argument
242 Register VReg0 = MIB->getOperand(0).getReg(); in selectMergeValues()
247 Register VReg1 = MIB->getOperand(1).getReg(); in selectMergeValues()
252 Register VReg2 = MIB->getOperand(2).getReg(); in selectMergeValues()
258 MIB->setDesc(TII.get(ARM::VMOVDRR)); in selectMergeValues()
259 MIB.add(predOps(ARMCC::AL)); in selectMergeValues()
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| D | ARMExpandPseudoInsts.cpp | 479 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandVLD() local
498 MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
502 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
504 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
506 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
508 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
512 MIB.add(MI.getOperand(OpIdx++)); in ExpandVLD()
515 MIB.add(MI.getOperand(OpIdx++)); in ExpandVLD()
516 MIB.add(MI.getOperand(OpIdx++)); in ExpandVLD()
540 MIB.add(AM6Offset); in ExpandVLD()
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| D | ARMLowOverheadLoops.cpp | 684 MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), in RevertWhile() local
686 MIB.add(MI->getOperand(0)); in RevertWhile()
687 MIB.addImm(0); in RevertWhile()
688 MIB.addImm(ARMCC::AL); in RevertWhile()
689 MIB.addReg(ARM::NoRegister); in RevertWhile()
695 MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(BrOpc)); in RevertWhile()
696 MIB.add(MI->getOperand(1)); // branch target in RevertWhile()
697 MIB.addImm(ARMCC::EQ); // condition code in RevertWhile()
698 MIB.addReg(ARM::CPSR); in RevertWhile()
713 MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), in RevertLoopDec() local
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| D | Thumb2SizeReduction.cpp | 480 auto MIB = BuildMI(MBB, MI, dl, TII->get(Entry.NarrowOpc1)) in ReduceLoadStore() local
488 MIB.setMemRefs(MI->memoperands()); in ReduceLoadStore()
491 MIB.setMIFlags(MI->getFlags()); in ReduceLoadStore()
582 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, TII->get(Opc)); in ReduceLoadStore() local
587 MIB.addReg(MI->getOperand(0).getReg(), RegState::Define | RegState::Dead); in ReduceLoadStore()
590 MIB.add(MI->getOperand(0)); in ReduceLoadStore()
591 MIB.add(MI->getOperand(1)); in ReduceLoadStore()
594 MIB.addImm(OffsetImm / Scale); in ReduceLoadStore()
599 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) | in ReduceLoadStore()
605 MIB.add(MI->getOperand(OpNum)); in ReduceLoadStore()
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| D | ThumbRegisterInfo.cpp | 172 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); in emitThumbRegPlusImmInReg() local
174 MIB = MIB.add(t1CondCodeOp()); in emitThumbRegPlusImmInReg()
176 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); in emitThumbRegPlusImmInReg()
178 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill); in emitThumbRegPlusImmInReg()
179 MIB.add(predOps(ARMCC::AL)); in emitThumbRegPlusImmInReg()
312 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(CopyOpc), DestReg); in emitThumbRegPlusImmediate() local
314 MIB = MIB.add(t1CondCodeOp()); in emitThumbRegPlusImmediate()
315 MIB.addReg(BaseReg, RegState::Kill); in emitThumbRegPlusImmediate()
317 MIB.addImm(CopyImm); in emitThumbRegPlusImmediate()
319 MIB.setMIFlags(MIFlags).add(predOps(ARMCC::AL)); in emitThumbRegPlusImmediate()
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| D | ARMCallLowering.cpp | 90 MachineInstrBuilder &MIB, CCAssignFn *AssignFn) in OutgoingValueHandler()
91 : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {} in OutgoingValueHandler()
125 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
184 MachineInstrBuilder &MIB; member
475 MachineInstrBuilder MIB, CCAssignFn *AssignFn) in CallReturnHandler()
476 : IncomingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {} in CallReturnHandler()
479 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
482 MachineInstrBuilder MIB; member
523 auto MIB = MIRBuilder.buildInstrNoInsert(CallOpcode); in lowerCall() local
527 MIB.add(predOps(ARMCC::AL)); in lowerCall()
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| D | ARMBaseInstrInfo.cpp | 776 MachineInstrBuilder MIB = in copyFromCPSR() local
782 MIB.addImm(0x800); in copyFromCPSR()
784 MIB.add(predOps(ARMCC::AL)) in copyFromCPSR()
796 MachineInstrBuilder MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Opc)); in copyToCPSR() local
799 MIB.addImm(0x800); in copyToCPSR()
801 MIB.addImm(8); in copyToCPSR()
803 MIB.addReg(SrcReg, getKillRegState(KillSrc)) in copyToCPSR()
808 void llvm::addUnpredicatedMveVpredNOp(MachineInstrBuilder &MIB) { in addUnpredicatedMveVpredNOp() argument
809 MIB.addImm(ARMVCC::None); in addUnpredicatedMveVpredNOp()
810 MIB.addReg(0); in addUnpredicatedMveVpredNOp()
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| D | ARMFastISel.cpp | 239 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
241 const MachineInstrBuilder &MIB,
284 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) { in AddOptionalDefs() argument
285 MachineInstr *MI = &*MIB; in AddOptionalDefs()
291 MIB.add(predOps(ARMCC::AL)); in AddOptionalDefs()
297 MIB.add(CPSR ? t1CondCodeOp() : condCodeOp()); in AddOptionalDefs()
298 return MIB; in AddOptionalDefs()
591 MachineInstrBuilder MIB; in ARMMaterializeGV() local
594 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), in ARMMaterializeGV()
597 MIB.addImm(Id); in ARMMaterializeGV()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 124 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) { in addDirectMem() argument
127 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); in addDirectMem()
143 addOffset(const MachineInstrBuilder &MIB, int Offset) { in addOffset() argument
144 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); in addOffset()
148 addOffset(const MachineInstrBuilder &MIB, const MachineOperand& Offset) { in addOffset() argument
149 return MIB.addImm(1).addReg(0).add(Offset).addReg(0); in addOffset()
157 addRegOffset(const MachineInstrBuilder &MIB, in addRegOffset() argument
159 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
164 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB, in addRegReg() argument
167 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
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| D | X86CallLowering.cpp | 100 MachineInstrBuilder &MIB, CCAssignFn *AssignFn) in OutgoingValueHandler()
101 : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB), in OutgoingValueHandler()
126 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
141 auto MIB = MIRBuilder.buildAnyExt(LLT::scalar(PhysRegSize), ValVReg); in assignValueToReg() local
142 ExtReg = MIB->getOperand(0).getReg(); in assignValueToReg()
178 MachineInstrBuilder &MIB; member
192 auto MIB = MIRBuilder.buildInstrNoInsert(X86::RET).addImm(0); in lowerReturn() local
218 OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, RetCC_X86); in lowerReturn()
223 MIRBuilder.insertInstr(MIB); in lowerReturn()
314 CCAssignFn *AssignFn, MachineInstrBuilder &MIB) in CallReturnHandler()
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| D | X86FixupBWInsts.cpp | 298 MachineInstrBuilder MIB = in tryReplaceLoad() local
303 MIB.add(MI->getOperand(i)); in tryReplaceLoad()
305 MIB.setMemRefs(MI->memoperands()); in tryReplaceLoad()
307 return MIB; in tryReplaceLoad()
333 MachineInstrBuilder MIB = in tryReplaceCopy() local
341 MIB.add(Op); in tryReplaceCopy()
343 return MIB; in tryReplaceCopy()
361 MachineInstrBuilder MIB = in tryReplaceExtend() local
366 MIB.add(MI->getOperand(i)); in tryReplaceExtend()
368 MIB.setMemRefs(MI->memoperands()); in tryReplaceExtend()
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| D | X86InstrInfo.cpp | 803 MachineInstrBuilder MIB = in convertToThreeAddressWithLEA() local
810 MIB.addReg(0).addImm(1ULL << ShAmt) in convertToThreeAddressWithLEA()
816 addRegOffset(MIB, InRegLEA, true, 1); in convertToThreeAddressWithLEA()
820 addRegOffset(MIB, InRegLEA, true, -1); in convertToThreeAddressWithLEA()
828 addRegOffset(MIB, InRegLEA, true, MI.getOperand(2).getImm()); in convertToThreeAddressWithLEA()
842 addRegReg(MIB, InRegLEA, true, InRegLEA, false); in convertToThreeAddressWithLEA()
850 BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA2); in convertToThreeAddressWithLEA()
851 InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY)) in convertToThreeAddressWithLEA()
854 addRegReg(MIB, InRegLEA, true, InRegLEA2, true); in convertToThreeAddressWithLEA()
862 MachineInstr *NewMI = MIB; in convertToThreeAddressWithLEA()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 190 MachineInstrBuilder &MIB, in CreateVirtualRegisters() argument
223 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
236 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
248 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
291 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, in AddRegisterOperand() argument
303 const MCInstrDesc &MCID = MIB->getDesc(); in AddRegisterOperand()
345 unsigned Idx = MIB->getNumOperands(); in AddRegisterOperand()
347 MIB->getOperand(Idx-1).isReg() && in AddRegisterOperand()
348 MIB->getOperand(Idx-1).isImplicit()) in AddRegisterOperand()
355 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) | in AddRegisterOperand()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | CSEMIRBuilder.cpp | 105 MachineInstrBuilder CSEMIRBuilder::memoizeMI(MachineInstrBuilder MIB, in memoizeMI() argument
107 assert(canPerformCSEForOpc(MIB->getOpcode()) && in memoizeMI()
109 MachineInstr *MIBInstr = MIB; in memoizeMI()
111 return MIB; in memoizeMI()
126 MachineInstrBuilder &MIB) { in generateCopiesIfRequired() argument
132 return buildCopy(Op.getReg(), MIB->getOperand(0).getReg()); in generateCopiesIfRequired()
134 return MIB; in generateCopiesIfRequired()
183 auto MIB = MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag); in buildInstr() local
186 getCSEInfo()->handleRemoveInst(&*MIB); in buildInstr()
187 return MIB; in buildInstr()
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| D | MachineIRBuilder.cpp | 79 MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode)); in buildInstrNoInsert() local
80 return MIB; in buildInstrNoInsert()
83 MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) { in insertInstr() argument
84 getMBB().insert(getInsertPt(), MIB); in insertInstr()
85 recordInsertion(MIB); in insertInstr()
86 return MIB; in insertInstr()
138 auto MIB = buildInstr(TargetOpcode::DBG_VALUE); in buildConstDbgValue() local
141 MIB.addCImm(CI); in buildConstDbgValue()
143 MIB.addImm(CI->getZExtValue()); in buildConstDbgValue()
145 MIB.addFPImm(CFP); in buildConstDbgValue()
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| D | CombinerHelper.cpp | 761 auto MIB = MIRBuilder.buildInstr(NewOpcode); in applyCombineIndexedLoadStore() local
763 MIB.addDef(MatchInfo.Addr); in applyCombineIndexedLoadStore()
764 MIB.addUse(MI.getOperand(0).getReg()); in applyCombineIndexedLoadStore()
766 MIB.addDef(MI.getOperand(0).getReg()); in applyCombineIndexedLoadStore()
767 MIB.addDef(MatchInfo.Addr); in applyCombineIndexedLoadStore()
770 MIB.addUse(MatchInfo.Base); in applyCombineIndexedLoadStore()
771 MIB.addUse(MatchInfo.Offset); in applyCombineIndexedLoadStore()
772 MIB.addImm(MatchInfo.IsPre); in applyCombineIndexedLoadStore()
935 static Register getMemsetValue(Register Val, LLT Ty, MachineIRBuilder &MIB) { in getMemsetValue() argument
936 MachineRegisterInfo &MRI = *MIB.getMRI(); in getMemsetValue()
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| D | IRTranslator.cpp | 436 bool IRTranslator::translateSwitch(const User &U, MachineIRBuilder &MIB) { in translateSwitch() argument
466 MIB.buildBr(*DefaultMBB); in translateSwitch()
502 if (!lowerSwitchWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB, MIB)) in translateSwitch()
512 MachineIRBuilder MIB(*MBB->getParent()); in emitJumpTable() local
513 MIB.setMBB(*MBB); in emitJumpTable()
514 MIB.setDebugLoc(CurBuilder->getDebugLoc()); in emitJumpTable()
519 auto Table = MIB.buildJumpTable(PtrTy, JT.JTI); in emitJumpTable()
520 MIB.buildBrJT(Table.getReg(0), JT.JTI, JT.Reg); in emitJumpTable()
526 MachineIRBuilder MIB(*HeaderBB->getParent()); in emitJumpTableHeader() local
527 MIB.setMBB(*HeaderBB); in emitJumpTableHeader()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 504 MachineInstrBuilder MIB = in selectG_MERGE_VALUES() local
508 MIB.addReg(Src.getReg(), getUndefRegState(Src.isUndef())); in selectG_MERGE_VALUES()
509 MIB.addImm(SubRegs[I]); in selectG_MERGE_VALUES()
1004 MachineInstrBuilder MIB = B.buildInstr(Opc) in selectStoreIntrinsic() local
1008 MIB.addUse(VOffset); in selectStoreIntrinsic()
1010 MIB.addUse(RSrc) in selectStoreIntrinsic()
1022 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectStoreIntrinsic()
1868 [=](MachineInstrBuilder &MIB) { MIB.add(Root); } in selectVCSRC()
1899 [=](MachineInstrBuilder &MIB) { MIB.add(Root); } in selectVSRC0()
1910 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3Mods0()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonOptAddrMode.cpp | 492 MachineInstrBuilder MIB; in changeLoad() local
498 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)); in changeLoad()
499 MIB.add(OldMI->getOperand(0)); in changeLoad()
500 MIB.add(OldMI->getOperand(2)); in changeLoad()
501 MIB.add(OldMI->getOperand(3)); in changeLoad()
502 MIB.add(ImmOp); in changeLoad()
509 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)) in changeLoad()
514 MIB.addGlobalAddress(GV, Offset, ImmOp.getTargetFlags()); in changeLoad()
521 LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n"); in changeLoad()
526 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)); in changeLoad()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64CallLowering.cpp | 120 MachineInstrBuilder MIB, CCAssignFn *AssignFn) in CallReturnHandler()
121 : IncomingArgHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {} in CallReturnHandler()
124 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
127 MachineInstrBuilder MIB; member
132 MachineInstrBuilder MIB, CCAssignFn *AssignFn, in OutgoingArgHandler()
135 : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB), in OutgoingArgHandler()
171 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
204 MachineInstrBuilder MIB; member
260 auto MIB = MIRBuilder.buildInstrNoInsert(AArch64::RET_ReallyLR); in lowerReturn() local
360 OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFn, AssignFn); in lowerReturn()
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| D | AArch64InstructionSelector.cpp | 260 MachineIRBuilder &MIB) const;
263 void renderTruncImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
265 void renderLogicalImm32(MachineInstrBuilder &MIB, const MachineInstr &I,
267 void renderLogicalImm64(MachineInstrBuilder &MIB, const MachineInstr &I,
625 MachineIRBuilder MIB(I); in selectSubregisterCopy() local
626 auto Copy = MIB.buildCopy({From}, {SrcReg}); in selectSubregisterCopy()
627 auto SubRegCopy = MIB.buildInstr(TargetOpcode::COPY, {To}, {}) in selectSubregisterCopy()
999 MachineIRBuilder MIB(I); in selectCompareBranch() local
1002 CCMI->getOperand(1), MIB)) in selectCompareBranch()
1006 MIB.buildInstr(AArch64::Bcc, {}, {}).addImm(CC).addMBB(DestMBB); in selectCompareBranch()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MicroMipsSizeReduction.cpp | 711 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID); in ReplaceInstruction() local
714 MIB.add(MI->getOperand(2)); in ReplaceInstruction()
717 MIB.add(MI->getOperand(0)); in ReplaceInstruction()
718 MIB.add(MI->getOperand(2)); in ReplaceInstruction()
723 MIB.add(MI->getOperand(0)); in ReplaceInstruction()
724 MIB.add(MI->getOperand(1)); in ReplaceInstruction()
725 MIB.add(MI->getOperand(2)); in ReplaceInstruction()
727 MIB.add(MI->getOperand(0)); in ReplaceInstruction()
728 MIB.add(MI->getOperand(2)); in ReplaceInstruction()
729 MIB.add(MI->getOperand(1)); in ReplaceInstruction()
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| D | Mips16InstrInfo.cpp | 90 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); in copyPhysReg() local
93 MIB.addReg(DestReg, RegState::Define); in copyPhysReg()
96 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
184 static void addSaveRestoreRegs(MachineInstrBuilder &MIB, in addSaveRestoreRegs() argument
198 MIB.addReg(Reg, Flags); in addSaveRestoreRegs()
218 MachineInstrBuilder MIB; in makeFrame() local
220 MIB = BuildMI(MBB, I, DL, get(Opc)); in makeFrame()
222 addSaveRestoreRegs(MIB, CSI); in makeFrame()
224 MIB.addReg(Mips::S2); in makeFrame()
226 MIB.addImm(FrameSize); in makeFrame()
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| D | MipsCallLowering.cpp | 123 MachineInstrBuilder &MIB) in CallReturnHandler() argument
124 : IncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {} in CallReturnHandler()
128 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
131 MachineInstrBuilder &MIB; member in __anon6bac01d40111::CallReturnHandler
228 MachineInstrBuilder &MIB) in OutgoingValueHandler() argument
229 : MipsHandler(MIRBuilder, MRI), MIB(MIB) {} in OutgoingValueHandler()
246 MachineInstrBuilder &MIB; member in __anon6bac01d40211::OutgoingValueHandler
283 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
569 MachineInstrBuilder MIB = MIRBuilder.buildInstrNoInsert( in lowerCall() local
571 MIB.addDef(Mips::SP, RegState::Implicit); in lowerCall()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrBuilder.h | 32 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0,
35 return MIB.addImm(Offset).addFrameIndex(FI);
37 return MIB.addFrameIndex(FI).addImm(Offset);
|