Home
last modified time | relevance | path

Searched refs:MM0 (Results 1 – 20 of 20) sorted by relevance

/third_party/mesa3d/src/mesa/x86/
D3dnow_xform4.S70 MOVQ ( REGIND(EAX), MM0 ) /* x1 | x0 */
76 MOVQ ( MM0, MM2 ) /* x1 | x0 */
79 PUNPCKLDQ ( MM0, MM0 ) /* x0 | x0 */
82 MOVQ ( MM0, MM1 ) /* x0 | x0 */
85 PFMUL ( REGIND(ECX), MM0 ) /* x0*m1 | x0*m0 */
101 PFADD ( MM0, MM2 )
159 MOVD ( REGIND(ECX), MM0 ) /* | m00 */
160 PUNPCKLDQ ( REGOFF(20, ECX), MM0 ) /* m11 | m00 */
181 PFMUL ( MM0, MM4 ) /* x1*m11 | x0*m00 */
251 MOVQ ( MM2, MM0 ) /* x1 | x0 */
[all …]
D3dnow_xform3.S70 MOVQ ( REGIND(EAX), MM0 ) /* x1 | x0 */
76 MOVQ ( MM0, MM1 ) /* x1 | x0 */
79 PUNPCKLDQ ( MM0, MM0 ) /* x0 | x0 */
85 MOVQ ( MM0, MM3 ) /* x0 | x0 */
89 PFMUL ( REGIND(ECX), MM0 ) /* x0*m1 | x0*m0 */
95 PFADD ( MM0, MM1 ) /* x0*m1+x1*m5 | x0*m0+x1*m4 */
151 MOVD ( REGIND(ECX), MM0 ) /* | m00 */
152 PUNPCKLDQ ( REGOFF(20, ECX), MM0 ) /* m11 | m00 */
173 PFMUL ( MM0, MM4 ) /* x1*m11 | x0*m00 */
241 MOVQ ( REGIND(EAX), MM0 ) /* x1 | x0 */
[all …]
D3dnow_xform2.S63 MOVD ( REGIND(ECX), MM0 ) /* | m00 */
64 PUNPCKLDQ ( REGOFF(16, ECX), MM0 ) /* m10 | m00 */
84 PFMUL ( MM0, MM6 ) /* x1*m10 | x0*m00 */
144 MOVD ( REGIND(ECX), MM0 ) /* | m00 */
145 PUNPCKLDQ ( REGOFF(20, ECX), MM0 ) /* m11 | m00 */
153 PFMUL ( MM0, MM4 ) /* x1*m11 | x0*m00 */
200 MOVD ( REGIND(ECX), MM0 ) /* | m00 */
201 PUNPCKLDQ ( REGOFF(16, ECX), MM0 ) /* m10 | m00 */
218 PFMUL ( MM0, MM6 ) /* x1*m10 | x0*m00 */
277 MOVD ( REGIND(ECX), MM0 ) /* | m00 */
[all …]
D3dnow_xform1.S63 MOVQ ( REGIND(ECX), MM0 ) /* m01 | m00 */
76 PFMUL ( MM0, MM4 ) /* x0*m01 | x0*m00 */
131 MOVD ( REGIND(EAX), MM0 ) /* | x0 */
134 MOVD ( MM0, REGIND(EDX) ) /* | r0 */
176 MOVD ( REGIND(ECX), MM0 ) /* | m00 */
185 PFMUL ( MM0, MM4 ) /* | x0*m00 */
234 MOVD ( REGIND(ECX), MM0 ) /* | m00 */
241 PFMUL ( MM0, MM4 ) /* 0 | x0*m00 */
288 MOVQ ( REGIND(ECX), MM0 ) /* m01 | m00 */
297 PFMUL ( MM0, MM4 ) /* x0*m01 | x0*m00 */
[all …]
Dmmx_blend.S272 PXOR ( MM0, MM0 ) /* 0x0000 | 0x0000 | 0x0000 | 0x0000 */
276 GMB_UNPACK( MM1, MM2, MM4, MM5, MM0 ) ;\
384 PXOR ( MM0, MM0 ) /* 0x0000 | 0x0000 | 0x0000 | 0x0000 */ ;\
392 GMB_UNPACK( MM1, MM2, MM4, MM5, MM0 ) ;\
Dassyntax.h215 #define MM0 %mm0 macro
/third_party/boost/libs/context/doc/
Drationale.qbk115 "The MMX and floating-point stack registers (MM0-MM7/ST0-ST7) are preserved across
120 "The 64-bit Microsoft compiler does not use ST(0)-ST(7)/MM0-MM7".
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86Instr3DNow.td77 Defs = [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
DX86CallingConv.td251 // MMX vector types are always returned in MM0. If the target doesn't have
252 // MM0, it doesn't support these vector types.
253 CCIfType<[x86mmx], CCAssignToReg<[MM0]>>,
804 CCAssignToReg<[MM0, MM1, MM2]>>>,
DX86InstrMMX.td155 Defs = [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
DX86RegisterInfo.td192 def MM0 : X86Reg<"mm0", 0>, DwarfRegNum<[41, 29, 29]>;
DX86InstrCompiler.td476 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
496 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h209 ENTRY(MM0) \
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp125 {codeview::RegisterId::MM0, X86::MM0}, in initLLVMToSEHAndCVRegMapping()
DX86InstComments.cpp209 if (X86::MM0 <= RegNo && RegNo <= X86::MM7) in getVectorRegSize()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenRegisterInfo.inc139 MM0 = 119,
1239 { X86::MM0 },
2106 X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7,
2756 { 41U, X86::MM0 },
2817 { 29U, X86::MM0 },
2862 { 29U, X86::MM0 },
2923 { 41U, X86::MM0 },
2984 { 29U, X86::MM0 },
3029 { 29U, X86::MM0 },
3075 { X86::MM0, 41U },
[all …]
DX86GenCallingConv.inc452 X86::MM0, X86::MM1, X86::MM2
2832 if (unsigned Reg = State.AllocateReg(X86::MM0)) {
DX86GenInstrInfo.inc16608 static const MCPhysReg ImplicitList39[] = { X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::…
16673 …X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7, X86::MM0, X86::MM1, X86::MM2…
16674 …X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7, X86::MM0, X86::MM1, X86::MM2…
DX86GenAsmMatcher.inc7188 case X86::MM0: OpKind = MCK_VR64; break;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/DebugInfo/CodeView/
DCodeViewRegisters.def142 CV_REGISTER(MM0, 146)