| /third_party/mesa3d/src/mesa/x86/ |
| D | 3dnow_xform4.S | 98 MOVQ ( MM6, MM7 ) /* x3 | x3 */
106 PFMUL ( REGOFF(56, ECX), MM7 ) /* x3*m15 | x3*m14 */
109 PFADD ( MM5, MM7 )
112 PFADD ( MM3, MM7 )
115 MOVQ ( MM7, REGOFF(-8, EDX) )
166 PXOR ( MM7, MM7 ) /* 0 | 0 */
187 PFSUBR ( MM7, MM3 ) /* | -x2 */
239 MOVD ( REGOFF(40, ECX), MM7 ) /* | m10 */
240 PUNPCKLDQ ( REGOFF(56, ECX), MM7 ) /* m14 | m10 */
275 PFMUL ( MM7, MM5 ) /* x3*m14 | x2*m10 */
[all …]
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| D | 3dnow_xform2.S | 82 MOVQ ( MM6, MM7 ) /* x1 | x0 */
85 PFMUL ( MM1, MM7 ) /* x1*m11 | x0*m01 */
87 PFACC ( MM7, MM6 ) /* x0*m01+x1*m11 | x0*x00+x1*m10 */
93 MOVQ ( MM6, MM7 ) /* x1 | x0 */
96 PFMUL ( MM3, MM7 ) /* x1*m13 | x0*m03 */
99 PFACC ( MM7, MM6 ) /* x0*m03+x1*m13 | x0*x02+x1*m12 */
216 MOVQ ( MM6, MM7 ) /* x1 | x0 */
219 PFMUL ( MM1, MM7 ) /* x1*m11 | x0*m01 */
221 PFACC ( MM7, MM6 ) /* x0*m01+x1*m11 | x0*x00+x1*m10 */
227 MOVQ ( MM6, MM7 ) /* x1 | x0 */
[all …]
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| D | mmx_blend.S | 322 MOVQ ( REGIND(ESP), MM7 ) ;\
329 PXOR ( MM7, MM3 ) /* unsigned -> signed */ ;\
330 PXOR ( MM7, MM4 ) /* unsigned -> signed */ ;\
354 MOVQ ( REGIND(ESP), MM7 ) ;\
361 PXOR ( MM7, MM3 ) /* unsigned -> signed */ ;\
362 PXOR ( MM7, MM4 ) /* unsigned -> signed */ ;\
387 MOVQ ( REGIND(ESP), MM7 ) ;\
393 GMB_MULT_GSR( MM1, MM2, MM4, MM5, MM7 ) ;\
|
| D | 3dnow_xform3.S | 170 PXOR ( MM7, MM7 ) /* 0 | 0 */
174 PFSUB ( MM5, MM7 ) /* | -x2 */
188 MOVD ( MM7, REGOFF(-4, EDX) ) /* write r3 */
232 MOVD ( REGOFF(8, ECX), MM7 ) /* | m2 */
233 PUNPCKLDQ ( REGOFF(24, ECX), MM7 ) /* m6 | m2 */
265 PFMUL ( MM7, MM0 ) /* x1*m6 | x0*m2 */
|
| D | assyntax.h | 222 #define MM7 %mm7 macro
|
| /third_party/boost/libs/context/doc/ |
| D | rationale.qbk | 115 "The MMX and floating-point stack registers (MM0-MM7/ST0-ST7) are preserved across
120 "The 64-bit Microsoft compiler does not use ST(0)-ST(7)/MM0-MM7".
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86Instr3DNow.td | 77 Defs = [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
|
| D | X86InstrMMX.td | 155 Defs = [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
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| D | X86RegisterInfo.td | 199 def MM7 : X86Reg<"mm7", 7>, DwarfRegNum<[48, 36, 36]>;
|
| D | X86InstrCompiler.td | 476 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
496 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 216 ENTRY(MM7)
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCTargetDesc.cpp | 132 {codeview::RegisterId::MM7, X86::MM7}, in initLLVMToSEHAndCVRegMapping()
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| D | X86InstComments.cpp | 209 if (X86::MM0 <= RegNo && RegNo <= X86::MM7) in getVectorRegSize()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/ |
| D | X86GenRegisterInfo.inc | 146 MM7 = 126,
1246 { X86::MM7 },
2106 X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7,
2763 { 48U, X86::MM7 },
2824 { 36U, X86::MM7 },
2869 { 36U, X86::MM7 },
2930 { 48U, X86::MM7 },
2991 { 36U, X86::MM7 },
3036 { 36U, X86::MM7 },
3082 { X86::MM7, 48U },
[all …]
|
| D | X86GenInstrInfo.inc | 16608 …X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::ST0, X86::ST1…
16673 …X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::XMM0, X86::XM…
16674 …X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::XMM0, X86::XM…
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| D | X86GenAsmMatcher.inc | 7195 case X86::MM7: OpKind = MCK_VR64; break;
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/DebugInfo/CodeView/ |
| D | CodeViewRegisters.def | 149 CV_REGISTER(MM7, 153)
|