Searched refs:NVISA_GV100_CHIPSET (Results 1 – 6 of 6) sorted by relevance
3221 op.lower_fdiv = (chipset >= NVISA_GV100_CHIPSET); in nvir_nir_shader_compiler_options()3228 op.lower_flrp16 = (chipset >= NVISA_GV100_CHIPSET); in nvir_nir_shader_compiler_options()3237 op.lower_bitfield_extract_to_shifts = (chipset >= NVISA_GV100_CHIPSET); in nvir_nir_shader_compiler_options()3239 op.lower_bitfield_insert_to_shifts = (chipset >= NVISA_GV100_CHIPSET); in nvir_nir_shader_compiler_options()3253 op.lower_isign = (chipset >= NVISA_GV100_CHIPSET); in nvir_nir_shader_compiler_options()3254 op.lower_fsign = (chipset >= NVISA_GV100_CHIPSET); in nvir_nir_shader_compiler_options()3296 op.lower_rotate = (chipset < NVISA_GV100_CHIPSET); in nvir_nir_shader_compiler_options()3301 ((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_imul64 : 0) | in nvir_nir_shader_compiler_options()3302 ((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_isign64 : 0) | in nvir_nir_shader_compiler_options()3304 ((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_imul_high64 : 0) | in nvir_nir_shader_compiler_options()[all …]
81 #define NVISA_GV100_CHIPSET 0x140 macro
270 const unsigned int bs = (chipset >= NVISA_GV100_CHIPSET) ? 16 : 0; in getFileSize()
902 if (prog->getTarget()->getChipset() >= NVISA_GV100_CHIPSET) in visit()1732 targ->getChipset() < NVISA_GV100_CHIPSET) { in handleCasExch()
2352 if (targ->getChipset() < NVISA_GV100_CHIPSET) { in texConstraintGM107()
688 if (info_out.target >= NVISA_GV100_CHIPSET) in nvc0_program_translate()