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Searched refs:NewOpc (Results 1 – 25 of 54) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86MCInstLower.cpp502 unsigned NewOpc; in Lower() local
505 case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break; in Lower()
506 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break; in Lower()
507 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break; in Lower()
508 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break; in Lower()
509 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break; in Lower()
510 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break; in Lower()
511 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break; in Lower()
512 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break; in Lower()
513 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break; in Lower()
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DX86EvexToVex.cpp147 static bool performCustomAdjustments(MachineInstr &MI, unsigned NewOpc) { in performCustomAdjustments() argument
148 (void)NewOpc; in performCustomAdjustments()
155 assert((NewOpc == X86::VPALIGNRrri || NewOpc == X86::VPALIGNRrmi) && in performCustomAdjustments()
171 assert((NewOpc == X86::VPERM2F128rr || NewOpc == X86::VPERM2I128rr || in performCustomAdjustments()
172 NewOpc == X86::VPERM2F128rm || NewOpc == X86::VPERM2I128rm) && in performCustomAdjustments()
259 unsigned NewOpc = I->VexOpcode; in CompressEvexToVexImpl() local
264 if (!performCustomAdjustments(MI, NewOpc)) in CompressEvexToVexImpl()
267 MI.setDesc(TII->get(NewOpc)); in CompressEvexToVexImpl()
DX86FixupLEAs.cpp577 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); in processInstrForSlow3OpLEA() local
583 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg) in processInstrForSlow3OpLEA()
589 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg) in processInstrForSlow3OpLEA()
615 unsigned NewOpc = in processInstrForSlow3OpLEA() local
617 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg) in processInstrForSlow3OpLEA()
621 unsigned NewOpc = getADDriFromLEA(MI.getOpcode(), Offset); in processInstrForSlow3OpLEA() local
622 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg) in processInstrForSlow3OpLEA()
648 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); in processInstrForSlow3OpLEA() local
649 NewMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), DestReg) in processInstrForSlow3OpLEA()
670 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); in processInstrForSlow3OpLEA() local
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DX86ISelDAGToDAG.cpp830 unsigned NewOpc; in PreprocessISelDAG() local
833 case ISD::FP_ROUND: NewOpc = X86ISD::VFPROUND; break; in PreprocessISelDAG()
834 case ISD::STRICT_FP_ROUND: NewOpc = X86ISD::STRICT_VFPROUND; break; in PreprocessISelDAG()
835 case ISD::STRICT_FP_TO_SINT: NewOpc = X86ISD::STRICT_CVTTP2SI; break; in PreprocessISelDAG()
836 case ISD::FP_TO_SINT: NewOpc = X86ISD::CVTTP2SI; break; in PreprocessISelDAG()
837 case ISD::STRICT_FP_TO_UINT: NewOpc = X86ISD::STRICT_CVTTP2UI; break; in PreprocessISelDAG()
838 case ISD::FP_TO_UINT: NewOpc = X86ISD::CVTTP2UI; break; in PreprocessISelDAG()
843 CurDAG->getNode(NewOpc, SDLoc(N), {N->getValueType(0), MVT::Other}, in PreprocessISelDAG()
847 CurDAG->getNode(NewOpc, SDLoc(N), N->getValueType(0), in PreprocessISelDAG()
863 unsigned NewOpc; in PreprocessISelDAG() local
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DX86InstructionSelector.cpp529 unsigned NewOpc = getLoadStoreOp(Ty, RB, Opc, MemOp.getAlignment()); in selectLoadStoreOp() local
530 if (NewOpc == Opc) in selectLoadStoreOp()
536 I.setDesc(TII.get(NewOpc)); in selectLoadStoreOp()
571 unsigned NewOpc = getLeaOP(Ty, STI); in selectFrameIndexOrGep() local
572 I.setDesc(TII.get(NewOpc)); in selectFrameIndexOrGep()
622 unsigned NewOpc = getLeaOP(Ty, STI); in selectGlobalValue() local
624 I.setDesc(TII.get(NewOpc)); in selectGlobalValue()
654 unsigned NewOpc; in selectConstant() local
657 NewOpc = X86::MOV8ri; in selectConstant()
660 NewOpc = X86::MOV16ri; in selectConstant()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsInstrInfo.cpp594 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc, in genInstrWithNewOpc() argument
616 switch (NewOpc) { in genInstrWithNewOpc()
618 NewOpc = Mips::BEQZC; in genInstrWithNewOpc()
621 NewOpc = Mips::BNEZC; in genInstrWithNewOpc()
624 NewOpc = Mips::BGEZC; in genInstrWithNewOpc()
627 NewOpc = Mips::BLTZC; in genInstrWithNewOpc()
630 NewOpc = Mips::BEQZC64; in genInstrWithNewOpc()
633 NewOpc = Mips::BNEZC64; in genInstrWithNewOpc()
638 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc)); in genInstrWithNewOpc()
644 if (NewOpc == Mips::JIC || NewOpc == Mips::JIALC || NewOpc == Mips::JIC64 || in genInstrWithNewOpc()
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DMipsSEInstrInfo.h96 unsigned NewOpc) const;
DMipsSEISelLowering.h78 SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
DMipsInstrInfo.h148 MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonRDFOpt.cpp224 unsigned OpNum, NewOpc; in rewrite() local
227 NewOpc = Hexagon::L2_loadri_io; in rewrite()
231 NewOpc = Hexagon::L2_loadrd_io; in rewrite()
235 NewOpc = Hexagon::V6_vL32b_ai; in rewrite()
239 NewOpc = Hexagon::S2_storeri_io; in rewrite()
243 NewOpc = Hexagon::S2_storerd_io; in rewrite()
247 NewOpc = Hexagon::V6_vS32b_ai; in rewrite()
273 MI.setDesc(HII.get(NewOpc)); in rewrite()
DHexagonGenPredicate.cpp388 unsigned NewOpc = getPredForm(Opc); in convertToPredForm() local
390 if (NewOpc == 0) { in convertToPredForm()
393 NewOpc = Hexagon::C2_not; in convertToPredForm()
396 NewOpc = TargetOpcode::COPY; in convertToPredForm()
423 MachineInstrBuilder MIB = BuildMI(B, MI, DL, TII->get(NewOpc), NewPR.R); in convertToPredForm()
DHexagonCopyToCombine.cpp868 unsigned NewOpc; in emitCombineRR() local
870 NewOpc = Hexagon::A2_combinew; in emitCombineRR()
873 NewOpc = Hexagon::V6_vcombine; in emitCombineRR()
877 BuildMI(*BB, InsertPt, DL, TII->get(NewOpc), DoubleDestReg) in emitCombineRR()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp1323 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode); in MergeBaseUpdateLSMultiple() local
1324 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc)) in MergeBaseUpdateLSMultiple()
1423 unsigned NewOpc; in MergeBaseUpdateLoadStore() local
1425 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::add); in MergeBaseUpdateLoadStore()
1427 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::sub); in MergeBaseUpdateLoadStore()
1431 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::add); in MergeBaseUpdateLoadStore()
1433 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::sub); in MergeBaseUpdateLoadStore()
1448 BuildMI(MBB, MBBI, DL, TII->get(NewOpc)) in MergeBaseUpdateLoadStore()
1458 if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) { in MergeBaseUpdateLoadStore()
1459 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg()) in MergeBaseUpdateLoadStore()
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DThumb2InstrInfo.cpp531 unsigned NewOpc = isSub ? IsSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12 in rewriteT2FrameIndex() local
533 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex()
564 unsigned NewOpc = Opcode; in rewriteT2FrameIndex() local
574 NewOpc = immediateOffsetOpcode(Opcode); in rewriteT2FrameIndex()
586 NewOpc = negativeOffsetOpcode(Opcode); in rewriteT2FrameIndex()
591 NewOpc = positiveOffsetOpcode(Opcode); in rewriteT2FrameIndex()
651 if (NewOpc != Opcode) in rewriteT2FrameIndex()
652 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex()
696 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc))); in rewriteT2FrameIndex()
DARMConstantIslandPass.cpp1773 unsigned NewOpc = 0; in optimizeThumb2Instructions() local
1780 NewOpc = ARM::tLEApcrel; in optimizeThumb2Instructions()
1787 NewOpc = ARM::tLDRpci; in optimizeThumb2Instructions()
1794 if (!NewOpc) in optimizeThumb2Instructions()
1807 U.MI->setDesc(TII->get(NewOpc)); in optimizeThumb2Instructions()
1824 unsigned NewOpc = 0; in optimizeThumb2Branches() local
1830 NewOpc = ARM::tB; in optimizeThumb2Branches()
1835 NewOpc = ARM::tBcc; in optimizeThumb2Branches()
1840 if (NewOpc) { in optimizeThumb2Branches()
1845 Br.MI->setDesc(TII->get(NewOpc)); in optimizeThumb2Branches()
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DARMInstructionSelector.cpp901 unsigned NewOpc = selectSimpleExtOpc(I.getOpcode(), SrcSize); in select() local
902 if (NewOpc == I.getOpcode()) in select()
904 I.setDesc(TII.get(NewOpc)); in select()
1097 const auto NewOpc = selectLoadStoreOpCode(I.getOpcode(), RegBank, ValSize); in select() local
1098 if (NewOpc == G_LOAD || NewOpc == G_STORE) in select()
1101 if (ValSize == 1 && NewOpc == Opcodes.STORE8) { in select()
1119 I.setDesc(TII.get(NewOpc)); in select()
1121 if (NewOpc == ARM::LDRH || NewOpc == ARM::STRH) in select()
DThumbRegisterInfo.cpp405 unsigned NewOpc = convertToNonSPOpcode(Opcode); in rewriteFrameIndex() local
406 if (NewOpc != Opcode && FrameReg != ARM::SP) in rewriteFrameIndex()
407 MI.setDesc(TII.get(NewOpc)); in rewriteFrameIndex()
DARMExpandPseudoInsts.cpp1273 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16; in ExpandMI() local
1274 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc), in ExpandMI()
1315 unsigned NewOpc; in ExpandMI() local
1317 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break; in ExpandMI()
1318 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break; in ExpandMI()
1319 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break; in ExpandMI()
1320 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break; in ExpandMI()
1323 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc), in ExpandMI()
1588 unsigned NewOpc = ARM::VLDMDIA; in ExpandMI() local
1590 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); in ExpandMI()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiMemAluCombiner.cpp252 unsigned NewOpc = mergedOpcode(MemInstr->getOpcode(), AluOffset.isImm()); in insertMergedInstruction() local
255 assert(NewOpc != 0 && "Unknown merged node opcode"); in insertMergedInstruction()
259 BuildMI(*BB, MemInstr, MemInstr->getDebugLoc(), TII->get(NewOpc)); in insertMergedInstruction()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64AdvSIMDScalarPass.cpp292 unsigned NewOpc = getTransformOpcode(OldOpc); in transformInstruction() local
293 assert(OldOpc != NewOpc && "transform an instruction to itself?!"); in transformInstruction()
362 BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), Dst) in transformInstruction()
DAArch64FrameLowering.cpp640 unsigned NewOpc; in convertCalleeSaveRestoreToSPPrePostIncDec() local
646 NewOpc = AArch64::STPXpre; in convertCalleeSaveRestoreToSPPrePostIncDec()
650 NewOpc = AArch64::STPDpre; in convertCalleeSaveRestoreToSPPrePostIncDec()
654 NewOpc = AArch64::STPQpre; in convertCalleeSaveRestoreToSPPrePostIncDec()
658 NewOpc = AArch64::STRXpre; in convertCalleeSaveRestoreToSPPrePostIncDec()
661 NewOpc = AArch64::STRDpre; in convertCalleeSaveRestoreToSPPrePostIncDec()
664 NewOpc = AArch64::STRQpre; in convertCalleeSaveRestoreToSPPrePostIncDec()
667 NewOpc = AArch64::LDPXpost; in convertCalleeSaveRestoreToSPPrePostIncDec()
671 NewOpc = AArch64::LDPDpost; in convertCalleeSaveRestoreToSPPrePostIncDec()
675 NewOpc = AArch64::LDPQpost; in convertCalleeSaveRestoreToSPPrePostIncDec()
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DAArch64CondBrTuning.cpp100 unsigned NewOpc = TII->convertToFlagSettingOpc(MI.getOpcode(), Is64Bit); in convertToFlagSetting() local
106 TII->get(NewOpc), NewDestReg); in convertToFlagSetting()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/AsmParser/
DX86AsmParser.cpp2957 unsigned NewOpc; in processInstruction() local
2960 case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break; in processInstruction()
2961 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break; in processInstruction()
2962 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break; in processInstruction()
2963 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break; in processInstruction()
2964 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break; in processInstruction()
2965 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break; in processInstruction()
2966 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break; in processInstruction()
2967 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break; in processInstruction()
2968 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break; in processInstruction()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp668 unsigned NewOpc = Node->getOpcode(); in PromoteFP_TO_INT() local
671 if (NewOpc == ISD::FP_TO_UINT && in PromoteFP_TO_INT()
673 NewOpc = ISD::FP_TO_SINT; in PromoteFP_TO_INT()
675 if (NewOpc == ISD::STRICT_FP_TO_UINT && in PromoteFP_TO_INT()
677 NewOpc = ISD::STRICT_FP_TO_SINT; in PromoteFP_TO_INT()
682 Promoted = DAG.getNode(NewOpc, dl, {NVT, MVT::Other}, in PromoteFP_TO_INT()
686 Promoted = DAG.getNode(NewOpc, dl, NVT, Node->getOperand(0)); in PromoteFP_TO_INT()
693 NewOpc = ISD::AssertZext; in PromoteFP_TO_INT()
695 NewOpc = ISD::AssertSext; in PromoteFP_TO_INT()
697 Promoted = DAG.getNode(NewOpc, dl, NVT, Promoted, in PromoteFP_TO_INT()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp741 int NewOpc; in commuteOpcode() local
744 NewOpc = AMDGPU::getCommuteRev(Opcode); in commuteOpcode()
745 if (NewOpc != -1) in commuteOpcode()
747 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1; in commuteOpcode()
750 NewOpc = AMDGPU::getCommuteOrig(Opcode); in commuteOpcode()
751 if (NewOpc != -1) in commuteOpcode()
753 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1; in commuteOpcode()
2343 unsigned NewOpc = isVGPRCopy ? AMDGPU::V_MOV_B32_e32 : AMDGPU::S_MOV_B32; in FoldImmediate() local
2347 NewOpc = AMDGPU::V_ACCVGPR_WRITE_B32; in FoldImmediate()
2349 UseMI.setDesc(get(NewOpc)); in FoldImmediate()
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