Searched refs:OP_EX2 (Results 1 – 15 of 15) sorted by relevance
| /third_party/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_target_gm107.cpp | 128 case OP_EX2: in isBarrierRequired()
259 case OP_EX2: in getLatency()
287 case OP_EX2: in getReadLatency()
|
| D | nv50_ir_target_nv50.cpp | 102 { OP_EX2, 0x0, 0x0, 0x0, 0x8, 0x0, 0x0, 0x0, 0x0 },
|
| D | nv50_ir_target_nvc0.cpp | 128 { OP_EX2, 0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
|
| D | nv50_ir_target_gv100.cpp | 267 case OP_EX2: in getOpInfo()
|
| D | nv50_ir_emit_gv100.cpp | 597 case OP_EX2 : mufu = 2; break; in emitMUFU()
1812 case OP_EX2: in emitInstruction()
|
| D | nv50_ir_emit_nv50.cpp | 1576 assert(subOp == 6 && i->op == OP_EX2); in emitSFnOp()
2056 case OP_EX2: in emitInstruction()
|
| D | nv50_ir.h | 92 OP_EX2, enumerator
|
| D | nv50_ir_from_tgsi.cpp | 3310 mkOp1(OP_EX2, TYPE_F32, dst0[0], val0); in handleInstruction()
3312 mkOp1(OP_EX2, TYPE_F32, dst0[2], src0); in handleInstruction()
3322 mkOp1(OP_EX2, TYPE_F32, dst0[1], val1); in handleInstruction()
|
| D | nv50_ir_lowering_nv50.cpp | 1376 i->op = OP_EX2; in handlePOW()
2208 case OP_EX2: in visit()
|
| D | nv50_ir_emit_gm107.cpp | 1448 case OP_EX2: mufu = 2; break; in emitMUFU()
3618 case OP_EX2: in emitInstruction()
|
| D | nv50_ir_lowering_nvc0.cpp | 3155 i->op = OP_EX2; in handlePOW()
3318 case OP_EX2: in visit()
|
| D | nv50_ir_peephole.cpp | 888 case OP_EX2: res.data.f32 = exp2f(imm.reg.data.f32); break; in unary()
1556 case OP_EX2: in opnd()
|
| D | nv50_ir_emit_gk110.cpp | 2644 case OP_EX2: in emitInstruction()
|
| D | nv50_ir_emit_nvc0.cpp | 2814 case OP_EX2: in emitInstruction()
|
| D | nv50_ir_from_nir.cpp | 427 return OP_EX2; in getOperation()
|