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Searched refs:OP_LOAD (Results 1 – 25 of 30) sorted by relevance

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/third_party/ltp/tools/sparse/sparse-src/
Dmemops.c75 if (one->opcode == OP_LOAD) in find_dominating_parents()
108 if (insn->bb && (insn->opcode != OP_LOAD && insn->opcode != OP_STORE)) in address_taken()
139 if (insn->opcode == OP_LOAD) { in simplify_loads()
161 if (dom->opcode == OP_LOAD) in simplify_loads()
214 if (dom->opcode == OP_LOAD) in try_to_kill_store()
Dssa.c109 case OP_LOAD: in rewrite_local_var()
174 case OP_LOAD: in ssa_convert_one_var()
233 case OP_LOAD: in matching_load()
262 case OP_LOAD: in ssa_rename_insn()
Dgraph.c87 case OP_LOAD: in graph_ep()
Dir.c162 case OP_LOAD: in validate_insn()
Dflow.c282 case OP_LOAD: in bb_has_side_effects()
452 case OP_LOAD: case OP_STORE: in dominates()
508 case OP_LOAD: in kill_dead_stores_bb()
Dliveness.c88 case OP_LOAD: in track_instruction_usage()
Dlinearize.c246 [OP_LOAD] = "load",
426 case OP_LOAD: in show_instruction()
974 insn = alloc_typed_instruction(OP_LOAD, ad->btype); in add_load()
2523 case OP_LOAD: in late_warnings()
Dexample.c67 [OP_LOAD] = "load",
1391 case OP_LOAD: in generate_one_insn()
Dsimplify.c372 case OP_LOAD: in kill_insn()
2775 case OP_LOAD: in simplify_instruction()
Dsparse-llvm.c1004 case OP_LOAD: in output_insn()
/third_party/mesa3d/src/gallium/drivers/nouveau/codegen/
Dnv50_ir_target_nvc0.cpp397 && i->op != OP_LOAD) in insnCanLoad()
449 (insn->op != OP_LOAD || insn->subOp != NV50_IR_SUBOP_LDC_IS)) in insnCanLoadOffset()
583 case OP_LOAD: in getLatency()
597 if (i->op == OP_LOAD) { in getLatency()
Dnv50_ir_target_nv50.cpp288 ((i->op != OP_ATOM && i->op != OP_LOAD) || in insnCanLoad()
410 if (i->op == OP_LOAD || i->op == OP_STORE || i->op == OP_ATOM) { in insnCanLoadOffset()
528 if (i->op == OP_LOAD) { in getLatency()
Dnv50_ir_target_gm107.cpp311 case OP_LOAD: in getReadLatency()
Dnv50_ir_peephole.cpp165 return ld && ld->op == OP_LOAD && ld->src(0).getFile() == FILE_MEMORY_CONST; in isCSpaceLoad()
185 (ld->op == OP_LOAD && in isAttribOrSharedLoad()
277 if (!ld || ld->fixed || (ld->op != OP_LOAD && ld->op != OP_MOV)) in visit()
279 if (ld->op == OP_LOAD && ld->subOp == NV50_IR_SUBOP_LOAD_LOCKED) in visit()
2947 if (insn->op == OP_LOAD || insn->op == OP_VFETCH) in getList()
2973 if (it->locked && insn->op != OP_LOAD && insn->op != OP_VFETCH) in findRecord()
3179 if (ldst->op == OP_LOAD || ldst->op == OP_VFETCH) { in runOpt()
3309 if (ld->op != OP_MOV && ld->op != OP_LOAD) in isConstantCondition()
3456 ((insn->op != OP_LOAD && insn->op != OP_STORE && insn->op != OP_ATOM) || in visit()
3772 if (op == OP_LOAD || op == OP_VFETCH || op == OP_ATOM) { in isResultEqual()
[all …]
Dnv50_ir_ra.cpp1756 ld = new_Instruction(func, OP_LOAD, ty); in unspill()
1765 Instruction *l = new_Instruction(func, OP_LOAD, TYPE_U32); in unspill()
2567 if (i->op == OP_LOAD || i->op == OP_VFETCH) { in visit()
2573 if (i->op == OP_LOAD && i->fixed && targ->getChipset() < 0xc0) { in visit()
2608 bool load = defi->op == OP_LOAD && in insertConstraintMove()
2630 mov->op = OP_LOAD; in insertConstraintMove()
Dnv50_ir_lowering_gm107.cpp104 case OP_LOAD: in visit()
Dnv50_ir_lowering_gv100.cpp315 case OP_LOAD: in visit()
Dnv50_ir_target_gv100.cpp295 case OP_LOAD: in getOpInfo()
Dnv50_ir_build_util.cpp111 Instruction *insn = new_Instruction(func, OP_LOAD, ty); in mkLoad()
Dnv50_ir_print.cpp668 case OP_LOAD: in print()
Dnv50_ir.h50 OP_LOAD, enumerator
Dnv50_ir_lowering_nvc0.cpp55 if (!ld || ld->fixed || (ld->op != OP_LOAD && ld->op != OP_MOV) || in handleDIV()
855 if (i->op == OP_LOAD && i->subOp == NV50_IR_SUBOP_LDC_IS) { in visit()
3341 case OP_LOAD: in visit()
Dnv50_ir_lowering_nv50.cpp1299 bld.mkOp1(OP_LOAD, TYPE_U16, x, in handleRDSV()
2226 case OP_LOAD: in visit()
/third_party/ltp/tools/sparse/sparse-src/Documentation/release-notes/
Dv0.5.0.rst87 * sparse-llvm: OP_LOAD
/third_party/ltp/tools/sparse/sparse-src/Documentation/
DIR.rst329 .. op:: OP_LOAD

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