/third_party/ffmpeg/libavcodec/x86/ |
D | qpeldsp.asm | 232 OP_MOV [r0], m1, m4 274 OP_MOV [r0+8], m0, m4 294 %define OP_MOV PUT_OP 297 %define OP_MOV AVG_OP 300 %define OP_MOV PUT_OP 357 OP_MOV [r0], m0, m4 367 %define OP_MOV PUT_OP 370 %define OP_MOV AVG_OP 373 %define OP_MOV PUT_OP 397 OP_MOV %5, m5, m7 [all …]
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D | h264_qpel_10bit.asm | 99 %define OP_MOV mova 105 %define OP_MOV AVG_MOV 174 OP_MOV [r0 ], m0 176 OP_MOV [r0+r2 ], m0 178 OP_MOV [r0+r2*2], m0 180 OP_MOV [r0+r3 ], m0 204 OP_MOV [r0 ], m0 205 OP_MOV [r0 +16], m1 208 OP_MOV [r0+r2 ], m0 209 OP_MOV [r0+r2+16], m1 [all …]
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/third_party/mesa3d/src/gallium/drivers/nouveau/codegen/ |
D | nv50_ir_build_util.cpp | 175 Instruction *insn = new_Instruction(func, OP_MOV, ty); in mkMov() 187 Instruction *insn = new_Instruction(func, OP_MOV, typeOfSize(src->reg.size)); in mkMovToReg() 200 Instruction *insn = new_Instruction(func, OP_MOV, typeOfSize(dst->reg.size)); in mkMovFromReg() 418 return mkOp1v(OP_MOV, TYPE_F32, dst ? dst : getScratch(), mkImm(f)); in loadImm() 424 return mkOp1v(OP_MOV, TYPE_F64, dst ? dst : getScratch(8), mkImm(d)); in loadImm() 430 return mkOp1v(OP_MOV, TYPE_U16, dst ? dst : getScratch(2), mkImm(u)); in loadImm() 436 return mkOp1v(OP_MOV, TYPE_U32, dst ? dst : getScratch(), mkImm(u)); in loadImm() 442 return mkOp1v(OP_MOV, TYPE_U64, dst ? dst : getScratch(8), mkImm(u)); in loadImm() 601 if (i->op == OP_MOV) { in split64BitOpPostRA() 611 case OP_MOV: srcNr = 1; break; in split64BitOpPostRA()
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D | nv50_ir_peephole.cpp | 52 if (op == OP_MOV || op == OP_UNION) { in isNop() 103 if (mov->op != OP_MOV || mov->fixed || !mov->getSrc(0)->asLValue()) in visit() 171 if (!ld || (ld->op != OP_MOV) || in isImmdLoad() 277 if (!ld || ld->fixed || (ld->op != OP_LOAD && ld->op != OP_MOV)) in visit() 341 } else if (insn->op == OP_MOV) { in visit() 413 if (i->op == OP_MOV || i->op == OP_CALL) in visit() 457 if (insn->op == OP_MOV) in findOriginForTestWithZero() 547 return OP_MOV; in getOp() 779 i->op = i->saturate ? OP_SAT : OP_MOV; in expr() 871 i->op = OP_MOV; in expr() [all …]
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D | nv50_ir_lowering_gm107.cpp | 60 bld.mkOp1(OP_MOV , TYPE_U32, src0, i->getSrc(0)); in handlePFETCH() 76 i->op = OP_MOV; in handleLOAD() 266 bld.mkOp1(OP_MOV , TYPE_U32, tmp2, i->getSrc(0)); in handlePFETCH()
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D | nv50_ir_lowering_helper.cpp | 40 case OP_MOV: in visit() 97 insn->op = OP_MOV; in handleCVT()
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D | nv50_ir_target_nvc0.cpp | 244 opInfo[i].pseudo = (i < OP_MOV); in initOpInfo() 693 if (a->op == OP_MOV || b->op == OP_MOV) in canDualIssue()
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D | nv50_ir_target_gm107.cpp | 221 case OP_MOV: in getLatency()
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D | nv50_ir_target_nv50.cpp | 121 OP_MOV, OP_ADD, OP_SUB, OP_MUL, OP_MAD, OP_SAD, OP_RCP, OP_LINTERP, in initOpInfo() 160 opInfo[i].pseudo = (i < OP_MOV); in initOpInfo()
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D | nv50_ir_target_gv100.cpp | 71 opInfo[i].pseudo = (i < OP_MOV); in initOpInfo() 316 case OP_MOV: return &opInfo_MOV; in getOpInfo()
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D | nv50_ir_ra.cpp | 518 mov = new_Instruction(func, OP_MOV, typeOfSize(tmp->reg.size)); in visit() 553 new_Instruction(func, OP_MOV, typeOfSize(tmp->reg.size)); in visit() 567 new_Instruction(func, OP_MOV, typeOfSize(tmp->reg.size)); in visit() 1161 case OP_MOV: in doCoalesce() 2606 bool imm = defi->op == OP_MOV && in insertConstraintMove() 2625 Instruction *mov = new_Instruction(func, OP_MOV, typeOfSize(size)); in insertConstraintMove() 2665 mov = new_Instruction(func, OP_MOV, typeOfSize(size)); in insertConstraintMoves()
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D | nv50_ir.h | 49 OP_MOV, // simple copy, no modifiers allowed enumerator 919 inline bool isPseudo() const { return op < OP_MOV; } in isPseudo()
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D | nv50_ir_emit_nv50.cpp | 397 assert(i->op == OP_MOV); in setSrcFileBits() 1118 const int s = (i->op == OP_MOV) ? 0 : 1; in emitAADD() 1946 case OP_MOV: in emitInstruction()
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D | nv50_ir_from_tgsi.cpp | 2169 mkOp1(OP_MOV, TYPE_U32, viewport, val); in storeDst() 3061 while (insn->op == OP_MOV) { in handleINTERP() 3276 mkOp1(OP_MOV, TYPE_U32, dst0[c], fetchSrc(0, c)); in handleInstruction() 3281 mkOp1(OP_MOV, TYPE_F32, dst0[c], val0); in handleInstruction() 3287 mkOp1(OP_MOV, TYPE_F32, dst0[c], val0); in handleInstruction() 3478 mkOp1(OP_MOV, TYPE_U32, dst0[0], zero); in handleInstruction()
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D | nv50_ir_lowering_nvc0.cpp | 55 if (!ld || ld->fixed || (ld->op != OP_LOAD && ld->op != OP_MOV) || in handleDIV() 870 if (i->op != OP_MOV && i->op != OP_PFETCH) in visit() 1441 bufq->op = OP_MOV; in handleBUFQ() 2946 i->op = OP_MOV; in handleRDSV() 3000 i->op = OP_MOV; in handleRDSV() 3170 i->op = OP_MOV; in handleEXPORT()
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D | nv50_ir_lowering_nv50.cpp | 573 bld.mkOp1(OP_MOV, ty, t, q)->setPredicate(CC_NS, cond); in handleDIV() 1159 bufq->op = OP_MOV; in handleBUFQ() 1393 i->op = OP_MOV; in handleEXPORT()
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D | nv50_ir_emit_nvc0.cpp | 417 i->op == OP_MOV || i->op == OP_PRESIN || i->op == OP_PREEX2); in emitForm_A() 2694 case OP_MOV: in emitInstruction() 2979 if (i->op == OP_MOV && i->lanes != 0xf) { in getMinEncodingSize()
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D | nv50_ir.cpp | 102 if (insn && insn->op == OP_MOV) { in getImmediate()
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D | nv50_ir_emit_gv100.cpp | 1886 case OP_MOV: in emitInstruction()
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D | nv50_ir_emit_gk110.cpp | 2518 case OP_MOV: in emitInstruction()
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D | nv50_ir_emit_gm107.cpp | 3471 case OP_MOV: in emitInstruction()
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