Searched refs:OpRC (Results 1 – 7 of 7) sorted by relevance
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | BreakFalseDeps.cpp | 125 const TargetRegisterClass *OpRC = in pickBestRegisterForUndef() local
132 !OpRC->contains(CurrMO.getReg())) in pickBestRegisterForUndef()
144 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef()
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| D | MachineInstr.cpp | 902 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI); in getRegClassConstraintEffect() local
908 if (OpRC) in getRegClassConstraintEffect()
909 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx); in getRegClassConstraintEffect()
912 } else if (OpRC) in getRegClassConstraintEffect()
913 CurRC = TRI->getCommonSubClass(CurRC, OpRC); in getRegClassConstraintEffect()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 312 const TargetRegisterClass *OpRC = nullptr; in AddRegisterOperand() local
314 OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF); in AddRegisterOperand()
316 if (OpRC) { in AddRegisterOperand()
318 = MRI->constrainRegClass(VReg, OpRC, MinRCSize); in AddRegisterOperand()
320 OpRC = TRI->getAllocatableClass(OpRC); in AddRegisterOperand()
321 assert(OpRC && "Constraints cannot be fulfilled for allocation"); in AddRegisterOperand()
322 Register NewVReg = MRI->createVirtualRegister(OpRC); in AddRegisterOperand()
381 const TargetRegisterClass *OpRC = in AddOperand() local
388 if (OpRC && IIRC && OpRC != IIRC && Register::isVirtualRegister(VReg)) { in AddOperand()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86SpeculativeLoadHardening.cpp | 2035 auto *OpRC = MRI->getRegClass(OpReg); in hardenLoadAddr() local
2036 Register TmpReg = MRI->createVirtualRegister(OpRC); in hardenLoadAddr()
2040 if (!Subtarget->hasVLX() && (OpRC->hasSuperClassEq(&X86::VR128RegClass) || in hardenLoadAddr()
2041 OpRC->hasSuperClassEq(&X86::VR256RegClass))) { in hardenLoadAddr()
2043 bool Is128Bit = OpRC->hasSuperClassEq(&X86::VR128RegClass); in hardenLoadAddr()
2057 Register VBStateReg = MRI->createVirtualRegister(OpRC); in hardenLoadAddr()
2077 } else if (OpRC->hasSuperClassEq(&X86::VR128XRegClass) || in hardenLoadAddr()
2078 OpRC->hasSuperClassEq(&X86::VR256XRegClass) || in hardenLoadAddr()
2079 OpRC->hasSuperClassEq(&X86::VR512RegClass)) { in hardenLoadAddr()
2081 bool Is128Bit = OpRC->hasSuperClassEq(&X86::VR128XRegClass); in hardenLoadAddr()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIFixSGPRCopies.cpp | 794 const TargetRegisterClass *OpRC = in processPHINode() local
796 if (!TRI->isSGPRClass(OpRC) && OpRC != &AMDGPU::VS_32RegClass && in processPHINode()
797 OpRC != &AMDGPU::VS_64RegClass) { in processPHINode()
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| D | SIInstrInfo.cpp | 4290 const TargetRegisterClass *OpRC = RI.getSubClassWithSubReg( in legalizeGenericOperand() local
4294 if (DstRC == OpRC) in legalizeGenericOperand()
4554 const TargetRegisterClass *OpRC = in legalizeOperands() local
4556 if (RI.hasVectorRegisters(OpRC)) { in legalizeOperands()
4557 VRC = OpRC; in legalizeOperands()
4559 SRC = OpRC; in legalizeOperands()
4616 const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg()); in legalizeOperands() local
4617 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(OpRC); in legalizeOperands()
4618 if (VRC == OpRC) in legalizeOperands()
5823 const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass); in findUsedSGPR() local
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonBitSimplify.cpp | 1876 auto *OpRC = HII.getRegClass(HII.get(Opc), OpNum, &HRI, MF); in validateReg() local
1878 return OpRC->hasSubClassEq(RRC); in validateReg()
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