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Searched refs:PIPE_CONTROL (Results 1 – 18 of 18) sorted by relevance

/third_party/libdrm/intel/tests/
Dgen6-3d.batch-ref.txt1 0x12300000: 0x7a000002: PIPE_CONTROL
5 0x12300010: 0x7a000002: PIPE_CONTROL
70 0x12300114: 0x7a000002: PIPE_CONTROL
130 0x12300204: 0x7a000002: PIPE_CONTROL
134 0x12300214: 0x7a000002: PIPE_CONTROL
138 0x12300224: 0x7a000002: PIPE_CONTROL
197 0x12300310: 0x7a000002: PIPE_CONTROL
201 0x12300320: 0x7a000002: PIPE_CONTROL
205 0x12300330: 0x7a000002: PIPE_CONTROL
279 0x12300458: 0x7a000002: PIPE_CONTROL
[all …]
Dgen7-3d.batch-ref.txt163 0x12300288: 0x7a000002: PIPE_CONTROL
167 0x12300298: 0x7a000002: PIPE_CONTROL
171 0x123002a8: 0x7a000002: PIPE_CONTROL
/third_party/FreeBSD/sys/compat/linuxkpi/common/include/linux/
Dusb.h177 #define PIPE_CONTROL 0x00 /* UE_CONTROL */ macro
192 usb_find_host_endpoint(dev, PIPE_CONTROL, (endpoint) | USB_DIR_OUT)
195 usb_find_host_endpoint(dev, PIPE_CONTROL, (endpoint) | USB_DIR_IN)
/third_party/mesa3d/src/intel/vulkan/
DgenX_query.c611 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in emit_ps_depth_count()
638 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in emit_query_pc_availability()
910 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in genX()
926 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in genX()
984 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in genX()
1046 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in genX()
1088 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in genX()
1106 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in genX()
1117 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in genX()
1195 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in genX()
[all …]
DgenX_cmd_buffer.c55 convert_pc_to_bits(struct GENX(PIPE_CONTROL) *pc) { in convert_pc_to_bits()
107 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in genX()
272 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in genX()
1898 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in emit_isp_disable()
1903 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in emit_isp_disable()
2071 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in genX()
2092 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in genX()
2104 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in genX()
2214 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe) { in genX()
2359 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe); in genX()
[all …]
Dgfx8_cmd_buffer.c147 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in genX()
194 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in genX()
/third_party/mesa3d/src/intel/blorp/
Dblorp_genX_exec.h246 blorp_emit(batch, GENX(PIPE_CONTROL), pc) { in emit_urb_config()
1612 blorp_emit(batch, GENX(PIPE_CONTROL), pipe) { in blorp_setup_binding_table()
1731 blorp_emit(batch, GENX(PIPE_CONTROL), pc) { in blorp_emit_depth_stencil_config()
1842 blorp_emit(batch, GENX(PIPE_CONTROL), pc) { in blorp_emit_gfx8_hiz_op()
1858 blorp_emit(batch, GENX(PIPE_CONTROL), pipe) { in blorp_update_clear_color()
1892 blorp_emit(batch, GENX(PIPE_CONTROL), pipe) { in blorp_update_clear_color()
2154 blorp_emit(batch, GENX(PIPE_CONTROL), pc) { in blorp_exec_compute()
/third_party/mesa3d/src/mesa/drivers/dri/i965/
DgenX_pipe_control.c465 brw_batch_emit(brw, GENX(PIPE_CONTROL), pc) { in genX()
/third_party/mesa3d/docs/relnotes/
D18.0.4.rst77 - i965,anv: Set the CS stall bit on the ISP disable PIPE_CONTROL
D20.0.2.rst102 - anv: Use the PIPE_CONTROL instead of bits for the CS stall W/A
D19.1.0.rst3006 - iris: Allow PIPE_CONTROL with Stall at Scoreboard and RT flush
3054 - iris: Disable a PIPE_CONTROL workaround on Icelake
3117 - iris: PIPE_CONTROL workarounds for GPGPU mode
3310 - i965: Use genxml for emitting PIPE_CONTROL.
3311 - i965: Reimplement all the PIPE_CONTROL rules.
D20.0.0.rst1635 - anv: Use PIPE_CONTROL flushes to implement the gen8 VF cache WA
2140 - genxml: add new Gen11+ PIPE_CONTROL field
2141 - iris: handle new PIPE_CONTROL field
D20.2.0.rst2183 - iris: Update cache coherency matrix on PIPE_CONTROL.
2191 - iris: Emit single render target flush PIPE_CONTROL on format mismatch.
3083 - intel/genxml: add PIPE_CONTROL command cache invalidate bit
D20.1.0.rst2358 - anv: Use the PIPE_CONTROL instead of bits for the CS stall W/A
D21.1.0.rst3160 - genxml: Add PIPE_CONTROL protected memory bits
/third_party/mesa3d/src/intel/common/
Dmi_builder.h1173 mi_builder_emit(b, GENX(PIPE_CONTROL), pc) { in mi_self_mod_barrier()
/third_party/mesa3d/src/gallium/drivers/iris/
Diris_state.c7842 iris_emit_cmd(batch, GENX(PIPE_CONTROL), pc) { in iris_emit_raw_pipe_control()
/third_party/mesa3d/src/gallium/drivers/crocus/
Dcrocus_state.c8856 crocus_emit_cmd(batch, GENX(PIPE_CONTROL), pc) {