Searched refs:PPR (Results 1 – 8 of 8) sorted by relevance
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.td | 823 def PPR : PPRClass<15>;
835 def PPRAsmOpAny : PPRAsmOperand<"PredicateAny", "PPR", 0>;
836 def PPRAsmOp8 : PPRAsmOperand<"PredicateB", "PPR", 8>;
837 def PPRAsmOp16 : PPRAsmOperand<"PredicateH", "PPR", 16>;
838 def PPRAsmOp32 : PPRAsmOperand<"PredicateS", "PPR", 32>;
839 def PPRAsmOp64 : PPRAsmOperand<"PredicateD", "PPR", 64>;
841 def PPRAny : PPRRegOp<"", PPRAsmOpAny, ElementSizeNone, PPR>;
842 def PPR8 : PPRRegOp<"b", PPRAsmOp8, ElementSizeB, PPR>;
843 def PPR16 : PPRRegOp<"h", PPRAsmOp16, ElementSizeH, PPR>;
844 def PPR32 : PPRRegOp<"s", PPRAsmOp32, ElementSizeS, PPR>;
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| D | AArch64SVEInstrInfo.td | 1092 def : Pat<(AArch64ptest (nxv16i1 PPR:$pg), (nxv16i1 PPR:$src)),
1093 (PTEST_PP PPR:$pg, PPR:$src)>;
1094 def : Pat<(AArch64ptest (nxv8i1 PPR:$pg), (nxv8i1 PPR:$src)),
1095 (PTEST_PP PPR:$pg, PPR:$src)>;
1096 def : Pat<(AArch64ptest (nxv4i1 PPR:$pg), (nxv4i1 PPR:$src)),
1097 (PTEST_PP PPR:$pg, PPR:$src)>;
1098 def : Pat<(AArch64ptest (nxv2i1 PPR:$pg), (nxv2i1 PPR:$src)),
1099 (PTEST_PP PPR:$pg, PPR:$src)>;
1161 def _default_z : Pat<(Ty (Load GPR64:$base, (PredTy PPR:$gp), (SVEDup0Undef))),
1162 (RegImmInst PPR:$gp, GPR64:$base, (i64 0))>;
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| D | SVEInstrFormats.td | 4796 …def : Pat<(uxtw_op (nxv4i32 ZPR:$data), (nxv4i1 PPR:$gp), GPR64sp:$base, (nxv4i32 ZPR:$offsets), v…
4797 … (!cast<Instruction>(NAME # _UXTW_SCALED) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
4798 …def : Pat<(sxtw_op (nxv4i32 ZPR:$data), (nxv4i1 PPR:$gp), GPR64sp:$base, (nxv4i32 ZPR:$offsets), v…
4799 … (!cast<Instruction>(NAME # _SXTW_SCALED) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
4816 …def : Pat<(uxtw_op (nxv2i64 ZPR:$data), (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$offsets), v…
4817 … (!cast<Instruction>(NAME # _UXTW_SCALED) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
4818 …def : Pat<(sxtw_op (nxv2i64 ZPR:$data), (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$offsets), v…
4819 … (!cast<Instruction>(NAME # _SXTW_SCALED) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
4836 …def : Pat<(uxtw_op (nxv2i64 ZPR:$data), (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$offsets), v…
4837 (!cast<Instruction>(NAME # _UXTW) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
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| D | AArch64FrameLowering.cpp | 1910 enum RegType { GPR, FPR64, FPR128, PPR, ZPR } Type; enumerator
1918 case PPR: in getScale()
1930 bool isScalable() const { return Type == PPR || Type == ZPR; } in isScalable()
1976 RPI.Type = RegPairInfo::PPR; in computeCalleeSaveRegisterPairs()
1999 case RegPairInfo::PPR: in computeCalleeSaveRegisterPairs()
2167 case RegPairInfo::PPR: in spillCalleeSavedRegisters()
2214 if (RPI.Type == RegPairInfo::ZPR || RPI.Type == RegPairInfo::PPR) in spillCalleeSavedRegisters()
2273 case RegPairInfo::PPR: in restoreCalleeSavedRegisters()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenRegisterInfo.inc | 2298 // PPR Register Class...
2299 const MCPhysReg PPR[] = {
2303 // PPR Bit set.
3439 { PPR, PPRBits, 284, 16, sizeof(PPRBits), AArch64::PPRRegClassID, 1, true },
5303 { 16, 16, 16, VTLists+34 }, // PPR
9349 { // PPR
20070 {1, 16}, // PPR
20202 "PPR",
20243 16, // 4: PPR
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| D | AArch64GenInstrInfo.inc | 19006 PPR = 411,
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| D | AArch64GenAsmMatcher.inc | 7477 MCK_PPR, // register class 'PPR'
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| /third_party/eudev/hwdb/ |
| D | 20-acpi-vendor.hwdb | 5400 acpi:PPR*:
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