| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | RegUsageInfoCollector.cpp | 155 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) { in runOnMachineFunction() local
157 if (SavedRegs.test(PReg)) in runOnMachineFunction()
161 if (!MRI->def_empty(PReg)) { in runOnMachineFunction()
162 for (MCRegAliasIterator AI(PReg, TRI, true); AI.isValid(); ++AI) in runOnMachineFunction()
170 if (UsedPhysRegsMask.test(PReg)) in runOnMachineFunction()
171 SetRegAsDefined(PReg); in runOnMachineFunction()
182 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) { in runOnMachineFunction()
183 if (MachineOperand::clobbersPhysReg(&(RegMask[0]), PReg)) in runOnMachineFunction()
184 dbgs() << printReg(PReg, TRI) << " "; in runOnMachineFunction()
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| D | RegisterUsageInfo.cpp | 95 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) { in print() local
96 if (MachineOperand::clobbersPhysReg(&(FPRMPair->second[0]), PReg)) in print()
97 OS << printReg(PReg, TRI) << " "; in print()
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| D | RegAllocPBQP.cpp | 614 unsigned PReg = RawPRegOrder[I]; in initializeGraph() local
615 if (MRI.isReserved(PReg)) in initializeGraph()
619 if (!RegMaskOverlaps.empty() && !RegMaskOverlaps.test(PReg)) in initializeGraph()
624 for (MCRegUnitIterator Units(PReg, &TRI); Units.isValid(); ++Units) { in initializeGraph()
634 VRegAllowed.push_back(PReg); in initializeGraph()
725 unsigned PReg = G.getNodeMetadata(NId).getAllowedRegs()[AllocOption - 1]; in mapPBQPToRegAlloc() local
727 << TRI.getName(PReg) << "\n"); in mapPBQPToRegAlloc()
728 assert(PReg != 0 && "Invalid preg selected."); in mapPBQPToRegAlloc()
729 VRM.assignVirt2Phys(VReg, PReg); in mapPBQPToRegAlloc()
753 unsigned PReg = MRI.getSimpleHint(LI.reg); in finalizeAlloc() local
[all …]
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| D | CallingConvLower.cpp | 252 for (MCPhysReg PReg : RemainingRegs) { in analyzeMustTailForwardedRegisters() local
253 unsigned VReg = MF.addLiveIn(PReg, RC); in analyzeMustTailForwardedRegisters()
254 Forwards.push_back(ForwardedRegister(VReg, PReg, RegVT)); in analyzeMustTailForwardedRegisters()
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| D | MachineFunction.cpp | 611 unsigned MachineFunction::addLiveIn(unsigned PReg, in addLiveIn() argument
614 unsigned VReg = MRI.getLiveInVirtReg(PReg); in addLiveIn()
623 assert((VRegRC == RC || (VRegRC->contains(PReg) && in addLiveIn()
629 MRI.addLiveIn(PReg, VReg); in addLiveIn()
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| D | MachineRegisterInfo.cpp | 460 unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const { in getLiveInVirtReg()
462 if (I->first == PReg) in getLiveInVirtReg()
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| D | MachineVerifier.cpp | 547 void MachineVerifier::report_context(MCPhysReg PReg) const { in report_context()
548 errs() << "- p. register: " << printReg(PReg, TRI) << '\n'; in report_context()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyReplacePhysRegs.cpp | 79 for (unsigned PReg = WebAssembly::NoRegister + 1; in runOnMachineFunction() local
80 PReg < WebAssembly::NUM_TARGET_REGS; ++PReg) { in runOnMachineFunction()
82 if (PReg == WebAssembly::VALUE_STACK || PReg == WebAssembly::ARGUMENTS) in runOnMachineFunction()
86 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(PReg); in runOnMachineFunction()
88 for (auto I = MRI.reg_begin(PReg), E = MRI.reg_end(); I != E;) { in runOnMachineFunction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonBitTracker.h | 57 unsigned getNextPhysReg(unsigned PReg, unsigned Width) const;
58 unsigned getVirtRegFor(unsigned PReg) const;
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| D | HexagonBitTracker.cpp | 1247 unsigned HexagonEvaluator::getNextPhysReg(unsigned PReg, unsigned Width) const { in getNextPhysReg() argument
1250 bool Is64 = DoubleRegsRegClass.contains(PReg); in getNextPhysReg()
1251 assert(PReg == 0 || Is64 || IntRegsRegClass.contains(PReg)); in getNextPhysReg()
1259 if (PReg == 0) in getNextPhysReg()
1267 if (Phys32[Idx32] == PReg) in getNextPhysReg()
1274 if (Phys64[Idx64] == PReg) in getNextPhysReg()
1286 unsigned HexagonEvaluator::getVirtRegFor(unsigned PReg) const { in getVirtRegFor()
1288 if (P.first == PReg) in getVirtRegFor()
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| D | HexagonBlockRanges.cpp | 280 unsigned PReg = *RC.begin(); in expandToSubRegs() local
281 MCSubRegIndexIterator I(PReg, &TRI); in expandToSubRegs()
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| D | HexagonInstrInfo.cpp | 1261 Register PReg = Op1.getReg(); in expandPostRAPseudo() local
1270 .addReg(PReg, S) in expandPostRAPseudo()
1279 .addReg(PReg, PState) in expandPostRAPseudo()
1295 Register PReg = Op1.getReg(); in expandPostRAPseudo() local
1306 .addReg(PReg, S) in expandPostRAPseudo()
1318 .addReg(PReg, PState) in expandPostRAPseudo()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 168 ForwardedRegister(unsigned VReg, MCPhysReg PReg, MVT VT) in ForwardedRegister()
169 : VReg(VReg), PReg(PReg), VT(VT) {} in ForwardedRegister()
171 MCPhysReg PReg; member
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| D | MachineFunction.h | 646 unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC);
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| D | MachineRegisterInfo.h | 950 unsigned getLiveInVirtReg(unsigned PReg) const;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64CallLowering.cpp | 411 MBB.addLiveIn(F.PReg); in handleMustTailForwardedRegisters()
412 MIRBuilder.buildCopy(Register(F.VReg), Register(F.PReg)); in handleMustTailForwardedRegisters()
877 Register ForwardedReg = F.PReg; in lowerTailCall()
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| D | AArch64ISelLowering.cpp | 4051 RegsToPass.emplace_back(F.PReg, Val); in LowerCall()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 1013 Register PReg = PMO.getReg(); in FormCandidates() local
1015 : TRI->getEncodingValue(PReg); in FormCandidates()
1024 PReg == getLoadStoreBaseOp(*MI).getReg()) in FormCandidates()
1035 if (PReg == ARM::SP || PReg == ARM::PC) in FormCandidates()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86FrameLowering.cpp | 2666 unsigned ScratchReg, SPReg, PReg, SPLimitOffset; in adjustForHiPEPrologue() local
2671 PReg = X86::RBP; in adjustForHiPEPrologue()
2677 PReg = X86::EBP; in adjustForHiPEPrologue()
2692 .addReg(ScratchReg), PReg, false, SPLimitOffset); in adjustForHiPEPrologue()
2701 .addReg(ScratchReg), PReg, false, SPLimitOffset); in adjustForHiPEPrologue()
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| D | X86ISelLowering.cpp | 4082 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val)); in LowerCall()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 1257 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) in addLiveIn() argument
1260 MF.getRegInfo().addLiveIn(PReg, VReg); in addLiveIn()
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