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Searched refs:Q0 (Results 1 – 25 of 62) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonVectorPrint.cpp76 || (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3); in isVecReg()
87 if (R >= Hexagon::Q0 && R <= Hexagon::Q3) { in getStringReg()
89 return S[R-Hexagon::Q0]; in getStringReg()
191 } else if (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3) { in runOnMachineFunction()
192 LLVM_DEBUG(dbgs() << "adding dump for Q" << Reg - Hexagon::Q0 << '\n'); in runOnMachineFunction()
DHexagonRegisterInfo.cpp77 Q0, Q1, Q2, Q3, 0 in getCallerSavedRegs()
DHexagonRegisterInfo.td222 def Q0 : Rq<0, "q0">, DwarfRegNum<[131]>;
323 (add Q0, Q1, Q2, Q3)> {
/third_party/ffmpeg/libavcodec/
Dcavsdsp.c41 #define Q0 p0_p[ 0*stride] macro
48 int q0 = Q0; in loop_filter_l2()
59 Q0 = (Q1 + q0 + s) >> 2; in loop_filter_l2()
62 Q0 = (2*Q1 + s) >> 2; in loop_filter_l2()
69 int q0 = Q0; in loop_filter_l1()
74 Q0 = av_clip_uint8(q0-delta); in loop_filter_l1()
76 delta = av_clip(((P0-P1)*3+P2-Q0+4)>>3, -tc, tc); in loop_filter_l1()
80 delta = av_clip(((Q1-Q0)*3+P0-Q2+4)>>3, -tc, tc); in loop_filter_l1()
89 int q0 = Q0; in loop_filter_c2()
99 Q0 = (Q1 + q0 + s) >> 2; in loop_filter_c2()
[all …]
Dhevcdsp_template.c1501 #define Q0 pix[0 * xstride] macro
1530 const int dq0 = abs(Q2 - 2 * Q1 + Q0); in FUNC()
1547 if (abs(P3 - P0) + abs(Q3 - Q0) < beta_3 && abs(P0 - Q0) < tc25 && in FUNC()
1557 const int q0 = Q0; in FUNC()
1567 … Q0 = q0 + av_clip(((p1 + 2 * p0 + 2 * q0 + 2 * q1 + q2 + 4) >> 3) - q0, -tc2, tc2); in FUNC()
1586 const int q0 = Q0; in FUNC()
1595 Q0 = av_clip_pixel(q0 - delta0); in FUNC()
1634 const int q0 = Q0; in FUNC()
1640 Q0 = av_clip_pixel(q0 - delta0); in FUNC()
1680 #undef Q0
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64CallingConvention.td104 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
106 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
108 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
111 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
113 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
146 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
148 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
150 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
153 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
155 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
[all …]
DAArch64CallingConvention.cpp35 static const MCPhysReg QRegList[] = {AArch64::Q0, AArch64::Q1, AArch64::Q2,
DAArch64AsmPrinter.cpp944 DestReg = AArch64::Q0 + (DestReg - AArch64::H0); in EmitFMov0()
946 DestReg = AArch64::Q0 + (DestReg - AArch64::S0); in EmitFMov0()
949 DestReg = AArch64::Q0 + (DestReg - AArch64::D0); in EmitFMov0()
DAArch64PBQPRegAlloc.cpp128 case AArch64::Q0: in isOdd()
/third_party/glslang/Test/
Dhlsl.gs-hs-mix.tesc95 float4 Q0 = mul(proj_matrix, float4(P0, 1.0));
100 vertex.PositionCS = Q0;
116 vertex.PositionCS = Q0;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMCallingConv.td77 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
84 CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>,
85 CCIfType<[f64], CCAssignToStackWithShadow<8, 4, [Q0, Q1, Q2, Q3]>>,
86 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 4, [Q0, Q1, Q2, Q3]>>,
97 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
142 CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>,
143 CCIfType<[f64], CCAssignToStackWithShadow<8, 8, [Q0, Q1, Q2, Q3]>>,
145 CCAssignToStackWithShadow<16, 16, [Q0, Q1, Q2, Q3]>>>,
146 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 8, [Q0, Q1, Q2, Q3]>>
223 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
[all …]
DARMCallingConv.cpp164 static const MCPhysReg QRegList[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3 };
/third_party/musl/porting/liteos_a/kernel/src/math/
Dexpm1l.c68 Q0 = -9.516813471998079611319047060563358064497E4L, variable
106 qx = (((( x + Q4) * x + Q3) * x + Q2) * x + Q1) * x + Q0; in expm1l()
/third_party/musl/src/math/
Dexpm1l.c68 Q0 = -9.516813471998079611319047060563358064497E4L, variable
106 qx = (((( x + Q4) * x + Q3) * x + Q2) * x + Q1) * x + Q0; in expm1l()
/third_party/boost/boost/move/detail/
Dfwd_macros.hpp98 #define BOOST_MOVE_FWDQ1 ::boost::forward<Q0>(q0)
194 #define BOOST_MOVE_DECLVALQ1 ::boost::move_detail::declval<Q0>()
305 #define BOOST_MOVE_FWD_INITQ1 m_q0(::boost::forward<Q0>(q0))
353 #define BOOST_MOVE_UREFQ1 BOOST_FWD_REF(Q0) q0
377 #define BOOST_MOVE_VALQ1 BOOST_FWD_REF(Q0) q0
403 #define BOOST_MOVE_CREFQ1 BOOST_MOVE_UNVOIDCREF(Q0) q0
427 #define BOOST_MOVE_CLASSQ1 class Q0
451 #define BOOST_MOVE_CLASSDFLTQ1 class Q0 = void
475 #define BOOST_MOVE_LAST_TARGQ1 Q0
500 #define BOOST_MOVE_TARGQ1 Q0
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenCallingConv.inc271 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
284 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
297 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
316 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
333 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
515 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
528 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
541 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
560 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
576 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
[all …]
/third_party/ffmpeg/libavcodec/arm/
Dvp8dsp_neon.S275 vabd.u8 q9, q3, q4 @ abs(P0-Q0)
277 vqadd.u8 q9, q9, q9 @ abs(P0-Q0) * 2
279 vqadd.u8 q11, q9, q10 @ (abs(P0-Q0)*2) + (abs(P1-Q1)/2)
281 vcle.u8 q8, q11, q14 @ (abs(P0-Q0)*2) + (abs(P1-Q1)/2) <= flim
285 vabd.u8 q13, q5, q4 @ abs(Q1-Q0)
289 vcle.u8 q9, q13, q15 @ abs(Q1-Q0) <= flim_I
299 vabd.u8 q9, q3, q4 @ abs(P0-Q0)
302 vqadd.u8 q9, q9, q9 @ abs(P0-Q0) * 2
306 vqadd.u8 q11, q9, q10 @ (abs(P0-Q0)*2) + (abs(P1-Q1)/2)
308 vcle.u8 q11, q11, q14 @ (abs(P0-Q0)*2) + (abs(P1-Q1)/2) <= flim_E
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenCallingConv.inc184 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
193 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
203 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
213 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
278 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
535 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
565 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
574 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
583 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
744 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
[all …]
/third_party/freetype/docs/reference/assets/images/icons/
Dgithub.f0b8504a.svg1 …-19.5 0-35.5-.75t-36.875-3.125-38.125-7.5-34.25-12.875T37 371.5t-21.5-28.75Q0 312 0 260q0-59.25 34…
/third_party/mesa3d/src/mesa/main/
Dtexcompress_astc.cpp175 uint8_t Q0 = (in >> (n)) & 0x1; in unpack_quint_block() local
190 q2 = CAT_BITS_3(Q0, Q4 & ~Q0, Q3 & ~Q0); in unpack_quint_block()
196 C = CAT_BITS_5(Q4, Q3, 0x1 & ~Q6, 0x1 & ~Q5, Q0); in unpack_quint_block()
199 C = CAT_BITS_5(Q4, Q3, Q2, Q1, Q0); in unpack_quint_block()
/third_party/ffmpeg/libavcodec/x86/
Dvp9lpf.asm326 %define Q0 dstq + 4* strideq + %1
341 %define Q0 rsp + 4*mmsize + %1
/third_party/glslang/Test/baseResults/
Dhlsl.gs-hs-mix.tesc.out393 0:95 'Q0' ( temp 4-component vector of float)
432 0:100 'Q0' ( temp 4-component vector of float)
476 0:116 'Q0' ( temp 4-component vector of float)
888 0:95 'Q0' ( temp 4-component vector of float)
927 0:100 'Q0' ( temp 4-component vector of float)
971 0:116 'Q0' ( temp 4-component vector of float)
1056 Name 194 "Q0"
1304 194(Q0): 193(ptr) Variable Function
1340 Store 194(Q0) 203
1359 223: 30(fvec4) Load 194(Q0)
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64InstPrinter.cpp1165 case AArch64::Q0: Reg = AArch64::Q1; break; in getNextVectorRegister()
1198 Reg = AArch64::Q0; in getNextVectorRegister()
1572 case 128: Base = AArch64::Q0; break; in printZPRasFPR()
DAArch64MCTargetDesc.cpp195 {codeview::RegisterId::ARM64_Q0, AArch64::Q0}, in initLLVMToCVRegMapping()
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/DartARM32/
Dassembler_arm.cc1276 EmitSIMDqqq(B25 | B24 | B23 | B10 | B8 | B7, kWordPair, qd, Q0, qm);
1292 qd, Q0, qm);
1298 qd, Q0, qm);
1304 Q0, qm); in vrecpeqs()
1313 qd, Q0, qm); in vrsqrteqs()
1359 EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B17 | B8 | B7, kByte, qd, Q0, qm); in vzipqw()

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