| /third_party/flutter/skia/third_party/externals/libjpeg-turbo/ |
| D | jdcoefct.c | 424 JLONG Q00, Q01, Q02, Q10, Q11, Q20, num; in decompress_smooth_data() local
486 Q10 = quanttbl->quantval[Q10_POS]; in decompress_smooth_data()
544 pred = (int)(((Q10 << 7) + num) / (Q10 << 8)); in decompress_smooth_data()
548 pred = (int)(((Q10 << 7) - num) / (Q10 << 8)); in decompress_smooth_data()
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| /third_party/libjpeg-turbo/ |
| D | jdcoefct.c | 424 JLONG Q00, Q01, Q02, Q10, Q11, Q20, num; in decompress_smooth_data() local
486 Q10 = quanttbl->quantval[Q10_POS]; in decompress_smooth_data()
544 pred = (int)(((Q10 << 7) + num) / (Q10 << 8)); in decompress_smooth_data()
548 pred = (int)(((Q10 << 7) - num) / (Q10 << 8)); in decompress_smooth_data()
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| /third_party/skia/third_party/externals/libjpeg-turbo/ |
| D | jdcoefct.c | 445 JLONG Q00, Q01, Q02, Q03 = 0, Q10, Q11, Q12 = 0, Q20, Q21 = 0, Q30 = 0, num; in decompress_smooth_data() local
528 Q10 = quanttbl->quantval[Q10_POS]; in decompress_smooth_data()
638 pred = (int)(((Q10 << 7) + num) / (Q10 << 8)); in decompress_smooth_data()
642 pred = (int)(((Q10 << 7) - num) / (Q10 << 8)); in decompress_smooth_data()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64PBQPRegAlloc.cpp | 133 case AArch64::Q10: in isOdd()
|
| D | AArch64SchedPredicates.td | 180 CheckRegOperand<0, Q10>,
|
| D | AArch64RegisterInfo.td | 398 def Q10 : AArch64Reg<10, "q10", [D10], ["v10", ""]>, DwarfRegAlias<B10>;
759 def Z10 : AArch64Reg<10, "z10", [Q10, Z10_HI]>, DwarfRegNum<[106]>;
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64MCTargetDesc.cpp | 205 {codeview::RegisterId::ARM64_Q10, AArch64::Q10}, in initLLVMToCVRegMapping()
|
| D | AArch64InstPrinter.cpp | 1174 case AArch64::Q9: Reg = AArch64::Q10; break; in getNextVectorRegister()
1175 case AArch64::Q10: Reg = AArch64::Q11; break; in getNextVectorRegister()
|
| /third_party/typescript/tests/cases/conformance/types/keyof/ |
| D | keyofAndIndexedAccess.ts | 58 type Q10 = Shape["name"]; // string alias
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/Disassembler/ |
| D | SparcDisassembler.cpp | 93 SP::Q2, SP::Q10, ~0U, ~0U,
|
| /third_party/typescript/tests/baselines/reference/ |
| D | keyofAndIndexedAccess.js | 56 type Q10 = Shape["name"]; // string
1151 declare type Q10 = Shape["name"];
|
| D | keyofAndIndexedAccess.symbols | 152 type Q10 = Shape["name"]; // string
153 >Q10 : Symbol(Q10, Decl(keyofAndIndexedAccess.ts, 52, 42))
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| D | keyofAndIndexedAccess.types | 130 type Q10 = Shape["name"]; // string
131 >Q10 : string
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcRegisterInfo.td | 276 def Q10 : Rq< 9, "F40", [D20, D21]>;
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 307 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
631 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/AsmParser/ |
| D | SparcAsmParser.cpp | 161 Sparc::Q8, Sparc::Q9, Sparc::Q10, Sparc::Q11,
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMRegisterInfo.td | 169 def Q10 : ARMReg<10, "q10", [D20, D21]>;
|
| D | ARMInstrThumb2.td | 3715 Q0, Q1, Q2, Q3, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenRegisterInfo.inc | 151 Q10 = 131,
2660 … AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArc…
2680 … AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArc…
3912 { AArch64::Q10, 74U },
4191 { AArch64::Q10, 74U },
20418 …AArch64::X28, AArch64::LR, AArch64::FP, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArc…
20420 …AArch64::X28, AArch64::LR, AArch64::FP, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArc…
20422 … AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArc…
20424 … AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArc…
20446 … AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArc…
[all …]
|
| D | AArch64GenSubtargetInfo.inc | 14025 || MI->getOperand(0).getReg() == AArch64::Q10
14179 || MI->getOperand(0).getReg() == AArch64::Q10
14333 || MI->getOperand(0).getReg() == AArch64::Q10
14544 || MI->getOperand(0).getReg() == AArch64::Q10
14585 || MI->getOperand(0).getReg() == AArch64::Q10
16554 || MI->getOperand(0).getReg() == AArch64::Q10
16595 || MI->getOperand(0).getReg() == AArch64::Q10
19661 || MI->getOperand(0).getReg() == AArch64::Q10
19815 || MI->getOperand(0).getReg() == AArch64::Q10
19969 || MI->getOperand(0).getReg() == AArch64::Q10
[all …]
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMMCCodeEmitter.cpp | 581 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11: in getMachineOpValue()
|
| /third_party/libsnd/docs/ |
| D | FAQ.md | 190 ## Q10 : Reading a 16 bit PCM file as normalised floats and then writing them back changes some sam…
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenRegisterInfo.inc | 86 Q10 = 66,
2087 … ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM:…
2107 …M::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12…
6245 …static const MCPhysReg AltOrder1[] = { ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, A…
6281 …static const MCPhysReg AltOrder1[] = { ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, A…
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 1366 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1385 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 2100 .Case("v10", AArch64::Q10) in MatchNeonVectorRegName()
|