Home
last modified time | relevance | path

Searched refs:R10 (Results 1 – 25 of 93) sorted by relevance

1234

/third_party/cmsis/CMSIS/DSP/Source/QuaternionMathFunctions/
Darm_rotation2quaternion_f32.c69 #define R10 vgetq_lane(q1,3) macro
113 q[3] = R10 - R01; in arm_rotation2quaternion_f32()
126 q[2] = R01 + R10; in arm_rotation2quaternion_f32()
139 q[1] = R01 + R10; in arm_rotation2quaternion_f32()
152 q[0] = R10 - R01; in arm_rotation2quaternion_f32()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/
DMSP430RegisterInfo.cpp43 MSP430::R8, MSP430::R9, MSP430::R10, in getCalleeSavedRegs()
48 MSP430::R8, MSP430::R9, MSP430::R10, in getCalleeSavedRegs()
53 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
59 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
DMSP430RegisterInfo.td63 def R10 : MSP430RegWithSubregs<10, "r10", [R10B]>;
81 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/
DXCoreRegisterInfo.td35 def R10 : Ri<10, "r10">, DwarfRegNum<[10]>;
48 R4, R5, R6, R7, R8, R9, R10,
55 R4, R5, R6, R7, R8, R9, R10,
DXCoreRegisterInfo.cpp215 XCore::R8, XCore::R9, XCore::R10, in getCalleeSavedRegs()
238 Reserved.set(XCore::R10); in getReservedRegs()
327 return TFI->hasFP(MF) ? XCore::R10 : XCore::SP; in getFrameRegister()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiRegisterInfo.td35 def RR1 : LanaiReg<10, "rr1", [R10]>, DwarfRegAlias<R10>;
50 R10, RR1, R11, RR2, // programmer controlled registers
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMCallingConv.td27 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
53 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
122 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
172 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
189 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
215 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
237 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
266 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
271 def CSR_Win_AAPCS_CFGuard_Check : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7,
282 R11, R10, R9, R8,
[all …]
DARMBaseRegisterInfo.h51 case R8: case R9: case R10: case R11: case R12: in isARMArea1Register()
63 case R8: case R9: case R10: case R11: case R12: in isARMArea2Register()
/third_party/ffmpeg/libavcodec/arm/
Dsimple_idct_arm.S104 ldr r10, =W5 @ R10=W5
119 @@ R5=b2, R6=ROWr16[0], R7=b3, R8=W1, R9=W3, R10=W5, R11=W7,
127 @@ R5=b2, R6=ROWr16[0], R7=b3, R8=W1, R9=W3, R10=W5, R11=W7,
159 @@ R5=b2, R6=ROWr16[0], R7=b3, R8 (free), R9 (free), R10 (free), R11 (free),
170 ldr r10, =W6 @ R10=W6
189 @@ R5=b2, R6=a0, R7=b3, R8=W2, R9=W4, R10=W6, R11 (free),
213 mulne r10, r8, r9 @ R10=W2*ROWr16[6]
225 @@ R5=b2, R6=a0, R7=b3, R8 (free), R9 (free), R10 (free), R11 (free),
239 ldr r10, =MASK_MSHW @ R10=0xFFFF0000
241 mvn r11, r10 @ R11= NOT R10= 0x0000FFFF
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCCallingConv.cpp38 PPC::R7, PPC::R8, PPC::R9, PPC::R10, in CC_PPC32_SVR4_Custom_AlignArgRegs()
63 PPC::R7, PPC::R8, PPC::R9, PPC::R10, in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
115 static const MCPhysReg LoRegList[] = { PPC::R4, PPC::R6, PPC::R8, PPC::R10 }; in CC_PPC32_SPE_CustomSplitFP64()
/third_party/libffi/src/x86/
Dwin64_intel.S63 mov R10, arg2 ; movq arg2, %r10
79 LEA R10, ffi_call_win64_tab ; leaq 0f(%rip), %r10
81 LEA R10, [R10 + RCX*8] ; leaq (%r10, %rcx, 8), %r10
83 JMP R10 ; jmp *%r10
/third_party/libunwind/src/x86_64/
Dinit.h59 c->dwarf.loc[R10] = REG_INIT_LOC(c, r10, R10); in common_init()
Dunwind_i.h49 #define R10 10 macro
DGos-freebsd.c124 c->dwarf.loc[R10] = DWARF_LOC (ucontext + UC_MCONTEXT_GREGS_R10, 0); in x86_64_handle_signal_frame()
136 c->dwarf.loc[RCX] = c->dwarf.loc[R10]; in x86_64_handle_signal_frame()
DGregs.c115 case UNW_X86_64_R10: loc = c->dwarf.loc[R10]; break; in tdep_access_reg()
/third_party/musl/arch/x32/bits/
Dreg.h10 #define R10 7 macro
/third_party/musl/arch/x86_64/bits/
Dreg.h10 #define R10 7 macro
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRRegisterInfo.td54 def R10 : AVRReg<10, "r10">, DwarfRegNum<[10]>;
100 def R11R10 : AVRReg<10, "r11:r10", [R10, R11]>, DwarfRegNum<[10]>;
120 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
127 add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/
DARCRegisterInfo.td39 def R10 : Core<10, "%r10">, DwarfRegNum<[10]>;
72 R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiBaseInfo.h66 case Lanai::R10: in getLanaiRegisterNumbering()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp166 {codeview::RegisterId::R10, X86::R10}, in initLLVMToSEHAndCVRegMapping()
647 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: in getX86SubSuperRegisterOrZero()
684 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: in getX86SubSuperRegisterOrZero()
720 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: in getX86SubSuperRegisterOrZero()
756 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: in getX86SubSuperRegisterOrZero()
757 return X86::R10; in getX86SubSuperRegisterOrZero()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
DBPFRegisterInfo.td50 R10 // Frame Ptr
DBPFRegisterInfo.cpp125 return BPF::R10; in getFrameRegister()
DBPFCallingConv.td48 def CSR : CalleeSavedRegs<(add R6, R7, R8, R9, R10)>;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenCallingConv.inc85 if (unsigned Reg = State.AllocateReg(ARM::R10)) {
255 if (unsigned Reg = State.AllocateReg(ARM::R10)) {
336 if (unsigned Reg = State.AllocateReg(ARM::R10)) {
482 ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11
623 if (unsigned Reg = State.AllocateReg(ARM::R10)) {
726 if (unsigned Reg = State.AllocateReg(ARM::R10)) {
802 if (unsigned Reg = State.AllocateReg(ARM::R10)) {

1234