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Searched refs:R12 (Results 1 – 25 of 81) sorted by relevance

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/third_party/ltp/tools/sparse/sparse-src/validation/
Drepeat.h13 #define R12(P, S) R9(P,S##0) R9(P,S##1) R9(P,S##2) R9(P,S##3) R9(P,S##4) R9(P,S##5) R9(P,S##… macro
14 #define R13(P, S) R12(P,S##0) R12(P,S##1)
15 #define R14(P, S) R12(P,S##0) R12(P,S##1) R12(P,S##2) R12(P,S##3)
16 #define R15(P, S) R12(P,S##0) R12(P,S##1) R12(P,S##2) R12(P,S##3) R12(P,S##4) R12(P,S##5) R12(P,S##…
/third_party/cmsis/CMSIS/DSP/Source/QuaternionMathFunctions/
Darm_rotation2quaternion_f32.c71 #define R12 vgetq_lane(q2,1) macro
111 q[1] = R21 - R12; in arm_rotation2quaternion_f32()
124 q[0] = R21 - R12; in arm_rotation2quaternion_f32()
141 q[3] = R12 + R21; in arm_rotation2quaternion_f32()
154 q[2] = R12 + R21; in arm_rotation2quaternion_f32()
/third_party/ffmpeg/libavcodec/arm/
Dsimple_idct_arm.S50 @@ R12 is another scratch register, so it should not be saved too
54 …14=&block[8*7], better start from the last row, and decrease the value until row=0, i.e. R12=block.
63 @@ at this point, R0=block, R14=&block[56], R12=__const_ptr_, R1-R11 free
68 ldr r1, [r14, #0] @ R1=(int32)(R12)[0]=ROWr32[0] (relative row cast to a 32b pointer)
69 ldr r2, [r14, #4] @ R2=(int32)(R12)[1]=ROWr32[1]
75 @@ at this point, R0=block, R14=&block[n], R12=__const_ptr_, R1=ROWr32[0], R2=ROWr32[1],
89 @@ R12=__const_ptr_, R14=&block[n]
120 @@ R12=__const_ptr_, R14=&block[n]
128 @@ R12=__const_ptr_, R14=&block[n]
160 @@ R12=__const_ptr_, R14=&block[n]
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/marl/src/
Dosfiber_asm_x64.h40 uintptr_t R12; member
60 static_assert(offsetof(marl_fiber_context, R12) == MARL_REG_R12,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/
DARCRegisterInfo.td42 def R12 : Core<12, "%r12">, DwarfRegNum<[12]>;
72 R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19,
78 (add R0, R1, R2, R3, R12, R13, R14, R15)>;
DARCFrameLowering.cpp159 StackSlotsUsedByFunclet = Last - ARC::R12; in emitPrologue()
271 StackSlotsUsedByFunclet = Last - ARC::R12; in emitEpilogue()
373 for (unsigned Which = Last; Which > ARC::R12; Which--) { in assignCalleeSavedSpillSlots()
386 if (I.getReg() > ARC::R12) in assignCalleeSavedSpillSlots()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/
DMSP430CallingConv.td18 // i16 are returned in registers R12, R13, R14, R15
19 CCIfType<[i16], CCAssignToReg<[R12, R13, R14, R15]>>
DMSP430RegisterInfo.cpp54 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
60 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
DMSP430RegisterInfo.td65 def R12 : MSP430RegWithSubregs<12, "r12", [R12B]>;
81 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
/third_party/libunwind/src/x86_64/
Dinit.h61 c->dwarf.loc[R12] = REG_INIT_LOC(c, r12, R12); in common_init()
DGget_save_loc.c43 case UNW_X86_64_R12: loc = c->dwarf.loc[R12]; break; in unw_get_save_loc()
Dunwind_i.h51 #define R12 12 macro
/third_party/boost/libs/context/src/asm/
Dontop_x86_64_ms_pe_masm.asm54 ; | limit | base | R12 | R13 |
126 mov [rsp+0d0h], r12 ; save R12
176 mov r12, [rsp+0d0h] ; restore R12
Djump_x86_64_ms_pe_masm.asm54 ; | limit | base | R12 | R13 |
126 mov [rsp+0d0h], r12 ; save R12
176 mov r12, [rsp+0d0h] ; restore R12
Dmake_x86_64_ms_pe_masm.asm54 ; | limit | base | R12 | R13 |
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86CallingConv.td64 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11, R12, R14, R15];
71 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15];
339 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>,
387 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>,
423 // Return: could return in any GP register save RSP and R12.
514 // A SwiftError is passed in R12.
515 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>,
584 CCIfType<[i64], CCAssignToReg<[RBX, R12, RBP, R15,
611 // A SwiftError is passed in R12.
612 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>,
[all …]
/third_party/musl/arch/x32/bits/
Dreg.h6 #define R12 3 macro
/third_party/musl/arch/x86_64/bits/
Dreg.h6 #define R12 3 macro
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRRegisterInfo.td56 def R12 : AVRReg<12, "r12">, DwarfRegNum<[12]>;
99 def R13R12 : AVRReg<12, "r13:r12", [R12, R13]>, DwarfRegNum<[12]>;
120 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
127 add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMBaseRegisterInfo.h51 case R8: case R9: case R10: case R11: case R12: in isARMArea1Register()
63 case R8: case R9: case R10: case R11: case R12: in isARMArea2Register()
DARMCallingConv.td164 // The 'nest' parameter, if any, is passed in R12.
165 CCIfNest<CCAssignToReg<[R12]>>,
308 : CalleeSavedRegs<(add LR, SP, (sub(sequence "R%u", 12, 1), R9, R12),
317 def CSR_iOS_CXX_TLS_PE : CalleeSavedRegs<(add LR, R12, R11, R7, R5, R4)>;
334 // of R8-R12, in addition to SP and LR. As before, mark LR for saving too.
DARMRegisterInfo.td91 def R12 : ARMReg<12, "r12">, DwarfRegNum<[12]>;
231 (add (trunc GPR, 8), R12, LR, (shl GPR, 8))];
243 (add (trunc GPRnopc, 8), R12, LR, (shl GPRnopc, 8))];
301 (add (trunc rGPR, 8), R12, LR, (shl rGPR, 8))];
327 def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R12)> {
343 def tGPREven : RegisterClass<"ARM", [i32], 32, (add R0, R2, R4, R6, R8, R10, R12, LR)> {
494 [(add R12), (add SP)]>;
501 // Register class representing a pair of even-odd GPRs, except (R12, SP).
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/InstCombine/
DInstCombineAndOrXor.cpp354 Value *R11, *R12; in getMaskedTypeForICmpPair() local
356 if (decomposeBitTestICmp(R1, R2, PredR, R11, R12, R2)) { in getMaskedTypeForICmpPair()
359 D = R12; in getMaskedTypeForICmpPair()
360 } else if (R12 == L11 || R12 == L12 || R12 == L21 || R12 == L22) { in getMaskedTypeForICmpPair()
361 A = R12; in getMaskedTypeForICmpPair()
370 if (!match(R1, m_And(m_Value(R11), m_Value(R12)))) { in getMaskedTypeForICmpPair()
374 R12 = Constant::getAllOnesValue(R1->getType()); in getMaskedTypeForICmpPair()
379 D = R12; in getMaskedTypeForICmpPair()
382 } else if (R12 == L11 || R12 == L12 || R12 == L21 || R12 == L22) { in getMaskedTypeForICmpPair()
383 A = R12; in getMaskedTypeForICmpPair()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiBaseInfo.h72 case Lanai::R12: in getLanaiRegisterNumbering()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp168 {codeview::RegisterId::R12, X86::R12}, in initLLVMToSEHAndCVRegMapping()
651 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: in getX86SubSuperRegisterOrZero()
688 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: in getX86SubSuperRegisterOrZero()
724 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: in getX86SubSuperRegisterOrZero()
760 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: in getX86SubSuperRegisterOrZero()
761 return X86::R12; in getX86SubSuperRegisterOrZero()

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