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Searched refs:R600 (Results 1 – 25 of 60) sorted by relevance

123

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600InstrInfo.cpp66 if ((R600::R600_Reg128RegClass.contains(DestReg) || in copyPhysReg()
67 R600::R600_Reg128VerticalRegClass.contains(DestReg)) && in copyPhysReg()
68 (R600::R600_Reg128RegClass.contains(SrcReg) || in copyPhysReg()
69 R600::R600_Reg128VerticalRegClass.contains(SrcReg))) { in copyPhysReg()
71 } else if((R600::R600_Reg64RegClass.contains(DestReg) || in copyPhysReg()
72 R600::R600_Reg64VerticalRegClass.contains(DestReg)) && in copyPhysReg()
73 (R600::R600_Reg64RegClass.contains(SrcReg) || in copyPhysReg()
74 R600::R600_Reg64VerticalRegClass.contains(SrcReg))) { in copyPhysReg()
81 buildDefaultInstruction(MBB, MI, R600::MOV, in copyPhysReg()
88 MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, R600::MOV, in copyPhysReg()
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DR600RegisterInfo.cpp37 reserveRegisterTuples(Reserved, R600::ZERO); in getReservedRegs()
38 reserveRegisterTuples(Reserved, R600::HALF); in getReservedRegs()
39 reserveRegisterTuples(Reserved, R600::ONE); in getReservedRegs()
40 reserveRegisterTuples(Reserved, R600::ONE_INT); in getReservedRegs()
41 reserveRegisterTuples(Reserved, R600::NEG_HALF); in getReservedRegs()
42 reserveRegisterTuples(Reserved, R600::NEG_ONE); in getReservedRegs()
43 reserveRegisterTuples(Reserved, R600::PV_X); in getReservedRegs()
44 reserveRegisterTuples(Reserved, R600::ALU_LITERAL_X); in getReservedRegs()
45 reserveRegisterTuples(Reserved, R600::ALU_CONST); in getReservedRegs()
46 reserveRegisterTuples(Reserved, R600::PREDICATE_BIT); in getReservedRegs()
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DR600ControlFlowFinalizer.cpp96 if (Opcode == R600::CF_ALU_PUSH_BEFORE && ST->hasCaymanISA() && in requiresWorkAroundForInst()
105 case R600::CF_ALU_PUSH_BEFORE: in requiresWorkAroundForInst()
106 case R600::CF_ALU_ELSE_AFTER: in requiresWorkAroundForInst()
107 case R600::CF_ALU_BREAK: in requiresWorkAroundForInst()
108 case R600::CF_ALU_CONTINUE: in requiresWorkAroundForInst()
170 case R600::CF_PUSH_EG: in pushBranch()
171 case R600::CF_ALU_PUSH_BEFORE: in pushBranch()
242 case R600::KILL: in IsTrivialInst()
243 case R600::RETURN: in IsTrivialInst()
255 Opcode = isEg ? R600::CF_TC_EG : R600::CF_TC_R600; in getHWInstrDesc()
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DR600ExpandSpecialInstrs.cpp98 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); in runOnMachineFunction()
102 DstOp.getReg(), R600::OQAP); in runOnMachineFunction()
103 DstOp.setReg(R600::OQAP); in runOnMachineFunction()
105 R600::OpName::pred_sel); in runOnMachineFunction()
107 R600::OpName::pred_sel); in runOnMachineFunction()
116 case R600::PRED_X: { in runOnMachineFunction()
124 R600::ZERO); // src1 in runOnMachineFunction()
127 TII->setImmOperand(*PredSet, R600::OpName::update_exec_mask, 1); in runOnMachineFunction()
129 TII->setImmOperand(*PredSet, R600::OpName::update_pred, 1); in runOnMachineFunction()
134 case R600::DOT_4: { in runOnMachineFunction()
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DR600EmitClauseMarkers.cpp54 case R600::INTERP_PAIR_XY: in OccupiedDwords()
55 case R600::INTERP_PAIR_ZW: in OccupiedDwords()
56 case R600::INTERP_VEC_LOAD: in OccupiedDwords()
57 case R600::DOT_4: in OccupiedDwords()
59 case R600::KILL: in OccupiedDwords()
79 if (MO.isReg() && MO.getReg() == R600::ALU_LITERAL_X) in OccupiedDwords()
91 case R600::PRED_X: in isALU()
92 case R600::INTERP_PAIR_XY: in isALU()
93 case R600::INTERP_PAIR_ZW: in isALU()
94 case R600::INTERP_VEC_LOAD: in isALU()
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DR600ClauseMergePass.cpp36 case R600::CF_ALU: in isCFAlu()
37 case R600::CF_ALU_PUSH_BEFORE: in isCFAlu()
87 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::COUNT)) in getCFAluSize()
94 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::Enabled)) in isCFAluEnabled()
100 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT); in cleanPotentialDisabledCFAlu()
119 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT); in mergeIfPossible()
127 if (RootCFAlu.getOpcode() == R600::CF_ALU_PUSH_BEFORE) in mergeIfPossible()
131 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_MODE0); in mergeIfPossible()
133 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_BANK0); in mergeIfPossible()
135 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_ADDR0); in mergeIfPossible()
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DR600MachineScheduler.cpp164 if (MO.isReg() && MO.getReg() == R600::ALU_LITERAL_X) in schedNode()
183 if (MI->getOpcode() != R600::COPY) in isPhysicalRegCopy()
226 case R600::PRED_X: in getAluKind()
228 case R600::INTERP_PAIR_XY: in getAluKind()
229 case R600::INTERP_PAIR_ZW: in getAluKind()
230 case R600::INTERP_VEC_LOAD: in getAluKind()
231 case R600::DOT_4: in getAluKind()
233 case R600::COPY: in getAluKind()
249 MI->getOpcode() == R600::GROUP_BARRIER) { in getAluKind()
260 case R600::sub0: in getAluKind()
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DR600Packetizer.cpp86 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::write); in getPreviousVector()
89 int DstIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::dst); in getPreviousVector()
95 Result[Dst] = R600::PS; in getPreviousVector()
98 if (BI->getOpcode() == R600::DOT4_r600 || in getPreviousVector()
99 BI->getOpcode() == R600::DOT4_eg) { in getPreviousVector()
100 Result[Dst] = R600::PV_X; in getPreviousVector()
103 if (Dst == R600::OQAP) { in getPreviousVector()
109 PVReg = R600::PV_X; in getPreviousVector()
112 PVReg = R600::PV_Y; in getPreviousVector()
115 PVReg = R600::PV_Z; in getPreviousVector()
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DR600ISelLowering.cpp59 addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass); in R600TargetLowering()
60 addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass); in R600TargetLowering()
61 addRegisterClass(MVT::v2f32, &R600::R600_Reg64RegClass); in R600TargetLowering()
62 addRegisterClass(MVT::v2i32, &R600::R600_Reg64RegClass); in R600TargetLowering()
63 addRegisterClass(MVT::v4f32, &R600::R600_Reg128RegClass); in R600TargetLowering()
64 addRegisterClass(MVT::v4i32, &R600::R600_Reg128RegClass); in R600TargetLowering()
288 return std::next(I)->getOpcode() == R600::RETURN; in isEOP()
304 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); in EmitInstrWithCustomInserter()
310 MI.getOpcode() == R600::LDS_CMPST_RET) in EmitInstrWithCustomInserter()
314 TII->get(R600::getLDSNoRetOp(MI.getOpcode()))); in EmitInstrWithCustomInserter()
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DAMDILCFGStructurizer.cpp435 if (I->getOpcode() == R600::PRED_X) { in reversePredicateSetter()
437 case R600::PRED_SETE_INT: in reversePredicateSetter()
438 I->getOperand(2).setImm(R600::PRED_SETNE_INT); in reversePredicateSetter()
440 case R600::PRED_SETNE_INT: in reversePredicateSetter()
441 I->getOperand(2).setImm(R600::PRED_SETE_INT); in reversePredicateSetter()
443 case R600::PRED_SETE: in reversePredicateSetter()
444 I->getOperand(2).setImm(R600::PRED_SETNE); in reversePredicateSetter()
446 case R600::PRED_SETNE: in reversePredicateSetter()
447 I->getOperand(2).setImm(R600::PRED_SETE); in reversePredicateSetter()
516 case R600::JUMP_COND: in getBranchNzeroOpcode()
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DR600.td1 //===-- R600.td - R600 Tablegen files ----------------------*- tablegen -*-===//
16 def R600 : Target {
21 let Namespace = "R600" in {
44 // Calling convention for R600
DR600OptimizeVectorRegisters.cpp76 assert(MI->getOpcode() == R600::REG_SEQUENCE); in RegSeqInfo()
156 case R600::R600_ExportSwz: in canSwizzle()
157 case R600::EG_ExportSwz: in canSwizzle()
210 Register DstReg = MRI->createVirtualRegister(&R600::R600_Reg128RegClass); in RebuildVector()
215 MachineInstr *Tmp = BuildMI(MBB, Pos, DL, TII->get(R600::INSERT_SUBREG), in RebuildVector()
231 BuildMI(MBB, Pos, DL, TII->get(R600::COPY), Reg).addReg(SrcVec); in RebuildVector()
351 if (MI.getOpcode() != R600::REG_SEQUENCE) { in runOnMachineFunction()
DR600Processors.td1 //===-- R600Processors.td - R600 Processor definitions --------------------===//
47 def FeatureR600 : R600SubtargetFeatureGeneration<"R600", "r600",
67 // Radeon HD 2000/3000 Series (R600).
DR600Schedule.td1 //===-- R600Schedule.td - R600 Scheduling definitions ------*- tablegen -*-===//
9 // R600 has a VLIW architecture. On pre-cayman cards there are 5 instruction
DR600InstrFormats.td1 //===-- R600InstrFormats.td - R600 Instruction Encodings ------------------===//
9 // R600 Instruction format definitions.
43 let Namespace = "R600";
189 XXX: R600 subtarget uses a slightly different encoding than the other
DR600Instructions.td1 //===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===//
9 // TableGen definitions for instructions which are available on R600 family
16 // FIXME: Should not be arbitrarily split from other R600 inst classes.
20 let Namespace = "R600";
89 usesCustomInserter = 1, Namespace = "R600" in {
377 // R600 SDNodes
380 let Namespace = "R600" in {
443 let Namespace = "R600" in {
686 // Common Instructions R600, R700, Evergreen, Cayman
691 let Namespace = "R600", usesCustomInserter = 1 in {
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/MCTargetDesc/
DR600MCCodeEmitter.cpp106 if (MI.getOpcode() == R600::RETURN || in encodeInstruction()
107 MI.getOpcode() == R600::FETCH_CLAUSE || in encodeInstruction()
108 MI.getOpcode() == R600::ALU_CLAUSE || in encodeInstruction()
109 MI.getOpcode() == R600::BUNDLE || in encodeInstruction()
110 MI.getOpcode() == R600::KILL) { in encodeInstruction()
115 if (!(STI.getFeatureBits()[R600::FeatureCaymanISA])) { in encodeInstruction()
148 if ((STI.getFeatureBits()[R600::FeatureR600ALUInst]) && in encodeInstruction()
/third_party/mesa3d/include/pci_ids/
Dr600_pci_ids.h1 CHIPSET(0x9400, R600_9400, R600)
2 CHIPSET(0x9401, R600_9401, R600)
3 CHIPSET(0x9402, R600_9402, R600)
4 CHIPSET(0x9403, R600_9403, R600)
5 CHIPSET(0x9405, R600_9405, R600)
6 CHIPSET(0x940A, R600_940A, R600)
7 CHIPSET(0x940B, R600_940B, R600)
8 CHIPSET(0x940F, R600_940F, R600)
/third_party/libdrm/radeon/
Dr600_pci_ids.h1 CHIPSET(0x9400, R600_9400, R600)
2 CHIPSET(0x9401, R600_9401, R600)
3 CHIPSET(0x9402, R600_9402, R600)
4 CHIPSET(0x9403, R600_9403, R600)
5 CHIPSET(0x9405, R600_9405, R600)
6 CHIPSET(0x940A, R600_940A, R600)
7 CHIPSET(0x940B, R600_940B, R600)
8 CHIPSET(0x940F, R600_940F, R600)
/third_party/mesa3d/src/gallium/drivers/r600/sb/
Dsb_context.cpp98 TRANSLATE_HW_CLASS(R600); in get_hw_class_name()
112 TRANSLATE_CHIP(R600); in get_hw_chip_name()
Dnotes.markdown11 - **R600\_DEBUG**
29 (R600\_SB=0), it's possible to use the following environment variables
32 - **R600\_SB\_DSKIP\_MODE** - allows to skip optimization for some
36 [R600\_SB\_DSKIP\_START; R600\_SB\_DSKIP\_END], that is,
39 [R600\_SB\_DSKIP\_START; R600\_SB\_DSKIP\_END]
41 - **R600\_SB\_DSKIP\_START** - start of the range (1-based)
43 - **R600\_SB\_DSKIP\_END** - end of the range (1-based)
Dsb_core.cpp294 TRANSLATE_CHIP(R600); in translate_chip()
329 case R600: return HW_CLASS_R600; in translate_chip_class()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/TargetInfo/
DAMDGPUTargetInfo.cpp32 RegisterTarget<Triple::r600, false> R600(getTheAMDGPUTarget(), "r600", in LLVMInitializeAMDGPUTargetInfo() local
/third_party/mesa3d/src/gallium/drivers/r600/sfn/
Dsfn_callstack.cpp94 case R600: in update_max_depth()
/third_party/mesa3d/src/gallium/drivers/r600/
Dr600_hw_context.c76 if (ctx->b.chip_class == R600) { in r600_need_cs_space()
163 (rctx->b.chip_class == R600 && rctx->b.flags & R600_CONTEXT_STREAMOUT_FLUSH)) { in r600_flush_emit()
288 if (ctx->b.chip_class == R600) { in r600_context_gfx_flush()
568 if (rctx->b.chip_class == R600) in r600_cp_dma_copy_buffer()

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