Searched refs:RCID (Results 1 – 10 of 10) sorted by relevance
134 bool isSGPRClassID(unsigned RCID) const { in isSGPRClassID() argument135 return isSGPRClass(getRegClass(RCID)); in isSGPRClassID()282 const TargetRegisterClass *getRegClass(unsigned RCID) const;
1830 SIRegisterInfo::getRegClass(unsigned RCID) const { in getRegClass()1831 switch ((int)RCID) { in getRegClass()1840 return AMDGPURegisterInfo::getRegClass(RCID); in getRegClass()
3829 unsigned RCID = Desc.OpInfo[OpNo].RegClass; in getOpRegClass() local3830 return RI.getRegClass(RCID); in getOpRegClass()3840 unsigned RCID = get(MI.getOpcode()).OpInfo[OpIdx].RegClass; in legalizeOpWithMove() local3841 const TargetRegisterClass *RC = RI.getRegClass(RCID); in legalizeOpWithMove()6278 const auto RCID = MI.getDesc().OpInfo[Idx].RegClass; in isBufferSMRD() local6279 return RI.getRegClass(RCID)->hasSubClassEq(&AMDGPU::SGPR_128RegClass); in isBufferSMRD()
595 unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); in getOperandRegClass() local597 Subtarget->getRegisterInfo()->getRegClass(RCID); in getOperandRegClass()
856 unsigned RCID; in getRegClassConstraint() local860 InlineAsm::hasRegClassConstraint(Flag, RCID)) in getRegClassConstraint()861 return TRI->getRegClass(RCID); in getRegClassConstraint()1631 unsigned RCID = 0; in print() local1633 InlineAsm::hasRegClassConstraint(Flag, RCID)) { in print()1635 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID)); in print()1637 OS << ":RC" << RCID; in print()
1083 unsigned getRegBitWidth(unsigned RCID) { in getRegBitWidth() argument1084 switch (RCID) { in getRegBitWidth()1139 unsigned RCID = Desc.OpInfo[OpNo].RegClass; in getRegOperandSize() local1140 return getRegBitWidth(MRI->getRegClass(RCID)) / 8; in getRegOperandSize()
586 unsigned getRegBitWidth(unsigned RCID);
246 bool isRegOrImmWithInputMods(unsigned RCID, MVT type) const { in isRegOrImmWithInputMods() argument247 return isRegClass(RCID) || isInlinableImm(type) || isLiteralImm(type); in isRegOrImmWithInputMods()365 bool isRegClass(unsigned RCID) const;369 bool isRegOrInlineNoMods(unsigned RCID, MVT type) const { in isRegOrInlineNoMods() argument370 return (isRegClass(RCID) || isInlinableImm(type)) && !hasModifiers(); in isRegOrInlineNoMods()1637 bool AMDGPUOperand::isRegClass(unsigned RCID) const { in isRegClass()1638 return isRegKind() && AsmParser->getMRI()->getRegClass(RCID).contains(getReg()); in isRegClass()2130 int RCID = getRegClass(RegKind, RegWidth); in getRegularReg() local2131 if (RCID == -1) in getRegularReg()2135 const MCRegisterClass RC = TRI->getRegClass(RCID); in getRegularReg()
579 int RCID = Desc.OpInfo[OpNo].RegClass; in printOperand() local580 unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID)); in printOperand()
1529 unsigned RCID; in handleSpecialFP() local1547 if (InlineAsm::hasRegClassConstraint(Flags, RCID)) { in handleSpecialFP()