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Searched refs:REG_A0 (Results 1 – 8 of 8) sorted by relevance

/third_party/musl/arch/riscv64/bits/
Dsignal.h44 #define REG_A0 10 macro
/third_party/mesa3d/src/freedreno/ir3/
Dir3_cp_postsched.c67 (instr->dsts[0]->num == regid(REG_A0, 0))) in has_conflicting_write()
Dir3_ra.h90 return reg_num(reg) != REG_A0 && reg_num(reg) != REG_P0; in def_is_gpr()
Dir3.h834 if (reg_num(dst) == REG_A0) in is_same_type_mov()
1094 if ((reg_num(dst) == REG_A0) || (dst->num == regid(REG_P0, 0))) in is_dest_gpr()
1113 return dst->num == regid(REG_A0, 0); in writes_addr0()
1124 return dst->num == regid(REG_A0, 1); in writes_addr1()
1148 return (reg->flags & IR3_REG_SHARED) || (reg_num(reg) == REG_A0) || in is_reg_special()
1182 if ((reg_num(r) == REG_A0) || (reg_num(r) == REG_P0)) in reg_gpr()
Dir3_context.c447 instr->dsts[0]->num = regid(REG_A0, 0); in create_addr0()
458 instr->dsts[0]->num = regid(REG_A0, 1); in create_addr1()
Dinstr-a3xx.h427 #define REG_A0 61 /* address register */ macro
Dir3_legalize.c215 if (last_rel && (reg->num == regid(REG_A0, 0))) { in legalize_block()
Dir3.c568 debug_assert(reg_num(addr->dsts[0]) == REG_A0); in ir3_instr_set_address()