Searched refs:REG_CLASS_WORK (Results 1 – 3 of 3) sorted by relevance
111 assert(classes[node] == REG_CLASS_WORK); in set_class()133 case REG_CLASS_WORK: in check_read_class()153 case REG_CLASS_WORK: in check_write_class()431 l->class_start[REG_CLASS_WORK] = 16 * 0; in allocate_registers()436 l->class_size[REG_CLASS_WORK] = 16 * work_count; in allocate_registers()450 l->class_start[REG_CLASS_TEXW] = l->class_start[REG_CLASS_WORK]; in allocate_registers()831 if (l->spill_class != REG_CLASS_WORK) { in mir_choose_spill_node()850 if (spill_class == REG_CLASS_WORK && ctx->inputs->is_blend) in mir_spill_register()859 bool is_special = spill_class != REG_CLASS_WORK; in mir_spill_register()1096 if (l->spill_class == REG_CLASS_WORK && uniforms > 8) { in mir_ra()
554 #define REG_CLASS_WORK 0 macro589 .no_spill = (1 << REG_CLASS_WORK) in v_load_store_scratch()
1386 stages[i]->no_spill |= (1 << REG_CLASS_WORK); in mir_schedule_alu()