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Searched refs:RMW (Results 1 – 25 of 28) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/
DAliasAnalysis.cpp604 ModRefInfo AAResults::getModRefInfo(const AtomicRMWInst *RMW, in getModRefInfo() argument
607 return getModRefInfo(RMW, Loc, AAQIP); in getModRefInfo()
610 ModRefInfo AAResults::getModRefInfo(const AtomicRMWInst *RMW, in getModRefInfo() argument
614 if (isStrongerThanMonotonic(RMW->getOrdering())) in getModRefInfo()
618 AliasResult AR = alias(MemoryLocation::get(RMW), Loc, AAQI); in getModRefInfo()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/
DInferAddressSpaces.cpp364 else if (auto *RMW = dyn_cast<AtomicRMWInst>(&I)) in collectFlatAddressExpressions() local
365 PushPtrOperand(RMW->getPointerOperand()); in collectFlatAddressExpressions()
772 if (auto *RMW = dyn_cast<AtomicRMWInst>(Inst)) in isSimplePointerUseValidToReplace() local
774 (VolatileIsAllowed || !RMW->isVolatile()); in isSimplePointerUseValidToReplace()
DLoopStrengthReduce.cpp827 } else if (AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(Inst)) { in isAddressUse() local
828 if (RMW->getPointerOperand() == OperandVal) in isAddressUse()
846 } else if (const AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(Inst)) { in getAccessType() local
847 AccessTy.AddrSpace = RMW->getPointerAddressSpace(); in getAccessType()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Analysis/
DAliasAnalysis.h575 ModRefInfo getModRefInfo(const AtomicRMWInst *RMW, const MemoryLocation &Loc);
578 ModRefInfo getModRefInfo(const AtomicRMWInst *RMW, const Value *P, in getModRefInfo() argument
580 return getModRefInfo(RMW, MemoryLocation(P, Size)); in getModRefInfo()
713 ModRefInfo getModRefInfo(const AtomicRMWInst *RMW, const MemoryLocation &Loc,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrAtomics.td519 // Truncating & zero-extending binary RMW patterns.
540 // Truncating & sign-extending binary RMW patterns.
543 // 64-bit) and select a zext RMW; the next instruction will be sext_inreg which
552 // 32->64 sext RMW gets selected as i32.atomic.rmw.***, i64.extend_i32_s
721 // Truncating & zero-extending ternary RMW patterns.
742 // Truncating & sign-extending ternary RMW patterns.
744 // zext RMW; the next instruction will be sext_inreg which is selected by
757 // 32->64 sext RMW gets selected as i32.atomic.rmw.***, i64.extend_i32_s
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Instrumentation/
DHWAddressSanitizer.cpp529 } else if (AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(I)) { in isInterestingMemoryAccess() local
532 *TypeSize = DL.getTypeStoreSizeInBits(RMW->getValOperand()->getType()); in isInterestingMemoryAccess()
534 PtrOperand = RMW->getPointerOperand(); in isInterestingMemoryAccess()
566 if (AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(I)) in getPointerOperandIndex() local
567 return RMW->getPointerOperandIndex(); in getPointerOperandIndex()
DAddressSanitizer.cpp1370 } else if (AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(I)) { in isInterestingMemoryAccess() local
1373 *TypeSize = DL.getTypeStoreSizeInBits(RMW->getValOperand()->getType()); in isInterestingMemoryAccess()
1375 PtrOperand = RMW->getPointerOperand(); in isInterestingMemoryAccess()
/third_party/mesa3d/docs/relnotes/
D20.1.6.rst93 - spirv: Don't emit RMW for vector indexing in shared or global
D20.1.0.rst3987 - radv: use RMW packets for updating the maximum sample distance
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUPromoteAlloca.cpp558 } else if (AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(UseInst)) { in collectUsesWithPtrTypes() local
559 if (RMW->isVolatile()) in collectUsesWithPtrTypes()
DSIISelLowering.cpp10961 SITargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const { in shouldExpandAtomicRMWInIR()
10962 switch (RMW->getOperation()) { in shouldExpandAtomicRMWInIR()
10964 Type *Ty = RMW->getType(); in shouldExpandAtomicRMWInIR()
10975 unsigned AS = RMW->getPointerAddressSpace(); in shouldExpandAtomicRMWInIR()
10978 return RMW->use_empty() ? AtomicExpansionKind::None : in shouldExpandAtomicRMWInIR()
10989 return AMDGPUTargetLowering::shouldExpandAtomicRMWInIR(RMW); in shouldExpandAtomicRMWInIR()
DAMDGPUISelLowering.cpp4708 AMDGPUTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const { in shouldExpandAtomicRMWInIR()
4709 switch (RMW->getOperation()) { in shouldExpandAtomicRMWInIR()
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/docs/
DDESIGN.rst63 | Read-modify-write (RMW) transform | |
522 - Read-modify-write (RMW) transformation
921 Subzero's ``O2`` recipe includes an early pass to find read-modify-write (RMW)
924 range ends after the RMW. Since liveness analysis is one of the most expensive
925 passes, it's not attractive to run it an extra time just for RMW analysis.
926 Instead, we essentially generate both the RMW and the non-RMW versions, and then
927 during lowering, the RMW version deletes itself if it finds x still live.
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/
DDESIGN.rst63 | Read-modify-write (RMW) transform | |
522 - Read-modify-write (RMW) transformation
921 Subzero's ``O2`` recipe includes an early pass to find read-modify-write (RMW)
924 range ends after the RMW. Since liveness analysis is one of the most expensive
925 passes, it's not attractive to run it an extra time just for RMW analysis.
926 Instead, we essentially generate both the RMW and the non-RMW versions, and then
927 during lowering, the RMW version deletes itself if it finds x still live.
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
DIceTargetLoweringX8632.cpp628 auto *RMW = in findRMW() local
631 Node->getInsts().insert(I3, RMW); in findRMW()
6758 void TargetX8632::lowerRMW(const InstX86FakeRMW *RMW) { in lowerRMW() argument
6765 if (!RMW->isLastUse(RMW->getBeacon())) in lowerRMW()
6767 Operand *Src = RMW->getData(); in lowerRMW()
6769 X86OperandMem *Addr = formMemoryOperand(RMW->getAddr(), Ty); in lowerRMW()
6777 switch (RMW->getOp()) { in lowerRMW()
6805 switch (RMW->getOp()) { in lowerRMW()
6835 if (const auto *RMW = llvm::dyn_cast<InstX86FakeRMW>(Instr)) { in lowerOther() local
6836 lowerRMW(RMW); in lowerOther()
DIceTargetLoweringX8664.cpp637 auto *RMW = in findRMW() local
640 Node->getInsts().insert(I3, RMW); in findRMW()
6099 void TargetX8664::lowerRMW(const InstX86FakeRMW *RMW) { in lowerRMW() argument
6106 if (!RMW->isLastUse(RMW->getBeacon())) in lowerRMW()
6108 Operand *Src = RMW->getData(); in lowerRMW()
6110 X86OperandMem *Addr = formMemoryOperand(RMW->getAddr(), Ty); in lowerRMW()
6112 switch (RMW->getOp()) { in lowerRMW()
6141 if (const auto *RMW = llvm::dyn_cast<InstX86FakeRMW>(Instr)) { in lowerOther() local
6142 lowerRMW(RMW); in lowerOther()
DIceTargetLoweringX8632.h285 void lowerRMW(const InstX86FakeRMW *RMW);
DIceTargetLoweringX8664.h281 void lowerRMW(const InstX86FakeRMW *RMW);
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DCodeGenPrepare.cpp4567 if (AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(UserI)) { in FindAllMemoryUses() local
4571 MemoryUses.push_back(std::make_pair(RMW, opNo)); in FindAllMemoryUses()
7125 if (AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(I)) { in optimizeInst() local
7126 unsigned AS = RMW->getPointerAddressSpace(); in optimizeInst()
7127 return optimizeMemoryInst(I, RMW->getPointerOperand(), in optimizeInst()
7128 RMW->getType(), AS); in optimizeInst()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86ScheduleBtVer2.td183 // A folded store needs a cycle on the SAGU for the store data, most RMW
184 // instructions don't need an extra uop. ALU RMW operations don't seem to
DX86Schedule.td154 def WriteXCHG : SchedWrite; // Compare+Exchange - TODO RMW support.
DX86SchedSandyBridge.td1025 def : SchedAlias<WriteBitTestRegLd, SBWriteResGroup100>; // TODO - this is incorrect - no RMW
DX86InstrArithmetic.td1206 // Patterns to recognize RMW ADC with loads in operand 1.
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DTargetLowering.h1837 virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const { in shouldExpandAtomicRMWInIR() argument
1838 return RMW->isFloatingPointOperation() ? in shouldExpandAtomicRMWInIR()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRInstrInfo.td1606 // Read-Write-Modify (RMW) instructions.

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