| /third_party/openssl/crypto/sha/asm/ |
| D | sha512-ppc.pl | 84 $ROR="rotrdi";
96 $ROR="rotrwi";
134 $ROR $a0,$e,$Sigma1[0]
135 $ROR $a1,$e,$Sigma1[1]
140 $ROR $a1,$a1,`$Sigma1[2]-$Sigma1[1]`
147 $ROR $a0,$a,$Sigma0[0]
148 $ROR $a1,$a,$Sigma0[1]
152 $ROR $a1,$a1,`$Sigma0[2]-$Sigma0[1]`
173 $ROR $a0,@X[($i+1)%16],$sigma0[0]
174 $ROR $a1,@X[($i+1)%16],$sigma0[1]
[all …]
|
| /third_party/openssl/crypto/sha/asm/arm32/ |
| D | sha1-armv4-large.S | 49 add r7,r7,r3,ror#27 @ E+=ROR(A,27)
55 add r7,r7,r3,ror#27 @ E+=ROR(A,27)
74 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
80 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
99 add r5,r5,r6,ror#27 @ E+=ROR(A,27)
105 add r5,r5,r6,ror#27 @ E+=ROR(A,27)
124 add r4,r4,r5,ror#27 @ E+=ROR(A,27)
130 add r4,r4,r5,ror#27 @ E+=ROR(A,27)
149 add r3,r3,r4,ror#27 @ E+=ROR(A,27)
155 add r3,r3,r4,ror#27 @ E+=ROR(A,27)
[all …]
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 37 ROR, enumerator
58 case AArch64_AM::ROR: return "ror"; in getShiftExtendName()
79 case 3: return AArch64_AM::ROR; in getShiftType()
107 case AArch64_AM::ROR: STEnc = 3; break; in getShifterImm()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedPredExynos.td | 143 // Identify EXTR as the alias for ROR (immediate).
|
| D | AArch64SchedPredicates.td | 51 def CheckShiftROR : CheckImmOperand_s<3, "AArch64_AM::ROR">;
|
| /third_party/mesa3d/src/gallium/drivers/vc4/ |
| D | vc4_qpu.h | 206 A_ALU2(ROR)
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRISelLowering.h | 41 ROR, ///< Bit rotate right. enumerator
|
| D | AVRISelLowering.cpp | 258 NODE(ROR); in getTargetNodeName()
320 Opc8 = AVRISD::ROR; in LowerShifts()
|
| /third_party/mesa3d/docs/relnotes/ |
| D | 20.2.4.rst | 84 - intel/compiler: Rotate instructions ROR and ROL cannot have source modifiers
|
| D | 19.3.3.rst | 104 - intel/fs/gen11+: Handle ROR/ROL in lower_simd_width().
|
| /third_party/python/Modules/ |
| D | sha256module.c | 116 #define ROR(x, y)\ macro
121 #define S(x, n) ROR((x),(n))
|
| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| D | IceInstARM32.def | 99 X(ROR, "ror") \
|
| /third_party/mesa3d/src/intel/tools/ |
| D | i965_lex.l | 118 ror { yylval.integer = BRW_OPCODE_ROR; return ROR; }
|
| D | i965_gram.y | 399 %token <integer> RET RNDD RNDE RNDU RNDZ ROL ROR
780 | ROR
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 455 ROR, enumerator
|
| /third_party/mesa3d/src/intel/compiler/ |
| D | brw_fs_builder.h | 640 ALU2(ROR) in ALU3()
|
| D | brw_eu.h | 244 ALU2(ROR) in ALU2()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86SchedSandyBridge.td | 955 "ROR(8|16|32|64)m(1|i)")>;
1000 "ROR(8|16|32|64)mCL",
|
| D | X86SchedBroadwell.td | 1107 "ROR(8|16|32|64)m(1|i)")>;
1184 "ROR(8|16|32|64)mCL",
|
| D | X86ScheduleAtom.td | 504 def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
|
| D | X86SchedHaswell.td | 1185 "ROR(8|16|32|64)m(1|i)")>;
1315 "ROR(8|16|32|64)mCL",
|
| D | X86SchedSkylakeClient.td | 1173 "ROR(8|16|32|64)m(1|i)")>;
1256 "ROR(8|16|32|64)mCL",
|
| /third_party/mesa3d/src/broadcom/compiler/ |
| D | v3d_compiler.h | 1270 VIR_A_ALU2(ROR) in VIR_A_ALU2()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 1209 ST == AArch64_AM::ASR || ST == AArch64_AM::ROR || in isShifter()
1315 ST == AArch64_AM::ASR || ST == AArch64_AM::ROR) && in isLogicalShifter()
2748 .Case("ror", AArch64_AM::ROR) in tryParseOptionalShiftExtend()
2770 ShOp == AArch64_AM::ASR || ShOp == AArch64_AM::ROR || in tryParseOptionalShiftExtend()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/DartARM32/ |
| D | assembler_arm.cc | 2509 mov(rd, Operand(rm, ROR, shift_imm.encoding()), cond); in Ror()
2513 mov(rd, Operand(rm, ROR, rs), cond); in Ror()
2517 mov(rd, Operand(rm, ROR, 0), cond); in Rrx()
|