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Searched refs:RW (Results 1 – 25 of 668) sorted by relevance

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/third_party/ffmpeg/libavfilter/
Df_perms.c74 enum perm { RO, RW }; enumerator
83 enum perm in_perm = av_frame_is_writable(frame) ? RW : RO; in filter_frame()
87 case MODE_TOGGLE: out_perm = in_perm == RO ? RW : RO; break; in filter_frame()
88 case MODE_RANDOM: out_perm = av_lfg_get(&s->lfg) & 1 ? RW : RO; break; in filter_frame()
90 case MODE_RW: out_perm = RW; break; in filter_frame()
98 if (in_perm == RO && out_perm == RW) { in filter_frame()
101 } else if (in_perm == RW && out_perm == RO) { in filter_frame()
109 if (in_perm == RW && out_perm == RO) in filter_frame()
/third_party/skia/third_party/externals/spirv-cross/shaders-no-opt/asm/comp/
Dbuffer-reference-aliased-block-name.nocompat.vk.asm.comp22 OpName %RW "Alias"
23 OpMemberName %RW 0 "v"
37 OpMemberDecorate %RW 0 Restrict
38 OpMemberDecorate %RW 0 Offset 0
39 OpDecorate %RW Block
59 %RW = OpTypeStruct %_runtimearr_v4float_0
60 %_ptr_PhysicalStorageBuffer_RW = OpTypePointer PhysicalStorageBuffer %RW
/third_party/skia/third_party/externals/spirv-cross/reference/opt/shaders/vulkan/comp/
Dbuffer-reference-decorations.nocompat.vk.comp.vk6 layout(buffer_reference) buffer RW;
13 layout(buffer_reference, std430) restrict buffer RW
26 RW rw;
/third_party/skia/third_party/externals/spirv-cross/reference/shaders/vulkan/comp/
Dbuffer-reference-decorations.nocompat.vk.comp.vk6 layout(buffer_reference) buffer RW;
13 layout(buffer_reference, std430) restrict buffer RW
26 RW rw;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonBitTracker.cpp94 uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub)); in mask() local
101 return IsSubLo ? BT::BitMask(0, RW-1) in mask()
102 : BT::BitMask(RW, 2*RW-1); in mask()
277 auto lo = [this] (const BT::RegisterCell &RC, uint16_t RW) in evaluate()
279 assert(RW <= RC.width()); in evaluate()
280 return eXTR(RC, 0, RW); in evaluate()
283 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW) in evaluate() argument
286 assert(RW <= W); in evaluate()
287 return eXTR(RC, W-RW, W); in evaluate()
347 uint16_t RW = W0; in evaluate() local
[all …]
DHexagonBitSimplify.cpp1550 unsigned RW = RC.width(); in findMatch() local
1551 if (W == RW) { in findMatch()
1565 if (W*2 != RW) in findMatch()
2396 unsigned RW = W; in simplifyExtractLow() local
2456 if (Len == RW) in simplifyExtractLow()
2479 if (SW < RW || (SW % RW) != 0) in simplifyExtractLow()
2487 unsigned OE = (Off+Len)/RW; in simplifyExtractLow()
2488 if (OE != Off/RW) { in simplifyExtractLow()
2495 Off = OE*RW; in simplifyExtractLow()
2518 Signed ? (RW == 32 ? Hexagon::S4_extract : Hexagon::S4_extractp) in simplifyExtractLow()
[all …]
/third_party/skia/third_party/externals/spirv-cross/shaders/vulkan/comp/
Dbuffer-reference-decorations.nocompat.vk.comp10 layout(std430, buffer_reference) restrict buffer RW
23 RW rw;
/third_party/vk-gl-cts/external/vulkancts/modules/vulkan/image/
DvktImageDepthStencilDescriptorTests.cpp109 RW = 2, // This always means a normal read/write depth/stencil attachment (NOT a storage image). enumerator
116 else if (access == AspectAccess::RW) stream << "rw"; in operator <<()
146 return ((aspect == VK_IMAGE_ASPECT_STENCIL_BIT) ? AspectAccess::RW : AspectAccess::RO); in getLegalAccess()
148 return ((aspect == VK_IMAGE_ASPECT_DEPTH_BIT) ? AspectAccess::RW : AspectAccess::RO); in getLegalAccess()
171 …const bool depthAsDSAttachment = (depthAccess == AspectAccess::RW || (depthAccess == AspectAccess… in incompatibleInputAttachmentAccess()
172 …const bool stencilAsDSAttachment = (stencilAccess == AspectAccess::RW || (stencilAccess == AspectA… in incompatibleInputAttachmentAccess()
250 if (depthAccess == AspectAccess::RW || stencilAccess == AspectAccess::RW) in getUsageFlags()
335 …return (depthAccess == AspectAccess::RW || (depthAccess == AspectAccess::RO && de::contains(begin(… in needsDepthTest()
341 …return (stencilAccess == AspectAccess::RW || (stencilAccess == AspectAccess::RO && de::contains(be… in needsStencilTest()
572 const auto stencilWrites = (m_params.stencilAccess == AspectAccess::RW); in iterate()
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/third_party/flutter/skia/third_party/externals/icu/source/data/region/
Drw.txt5 RW{"U Rwanda"}
Dzh_Hant_HK.txt70 RW{"盧旺達"}
Dyi.txt182 RW{"רוואַנדע"}
Dshi.txt176 RW{"ⵔⵡⴰⵏⴷⴰ"}
/third_party/skia/third_party/externals/icu/source/data/region/
Drw.txt7 RW{"U Rwanda"}
Dzh_Hant_HK.txt72 RW{"盧旺達"}
/third_party/icu/icu4c/source/data/region/
Drw.txt7 RW{"U Rwanda"}
Dzh_Hant_HK.txt72 RW{"盧旺達"}
/third_party/typescript_eslint/packages/experimental-utils/src/ts-eslint-scope/
DReference.ts39 RW: 0x3; constant
/third_party/python/Lib/test/
Dtest_enum.py2229 RW = 2 variable in TestFlag.Open
2313 RW = Perm.R | Perm.W
2317 values = list(Perm) + [RW, RX, WX, RWX, Perm(0)]
2344 RW = Perm.R | Perm.W
2348 values = list(Perm) + [RW, RX, WX, RWX, Perm(0)]
2487 RW = R | W
2491 self.assertTrue(R in RW)
2494 self.assertTrue(W in RW)
2502 self.assertFalse(X in RW)
2678 RW = 2 variable in TestIntFlag.Open
[all …]
/third_party/elfio/tests/elf_examples/
Dhello_32.txt65 LOAD 0x00048c 0x0804948c 0x0804948c 0x000fc 0x00104 RW 0x1000
66 DYNAMIC 0x0004a0 0x080494a0 0x080494a0 0x000c8 0x000c8 RW 0x4
68 GNU_STACK 0x000000 0x00000000 0x00000000 0x00000 0x00000 RW 0x4
Dhello_64.txt101 0x00000000000001ec 0x0000000000000200 RW 200000
103 0x0000000000000190 0x0000000000000190 RW 8
109 0x0000000000000000 0x0000000000000000 RW 8
Dtest_ppc.txt68 LOAD 0x000acc 0x10010acc 0x10010acc 0x00140 0x001d8 RW 0x10000
69 DYNAMIC 0x000aec 0x10010aec 0x10010aec 0x000e8 0x000e8 RW 0x4
72 GNU_STACK 0x000000 0x00000000 0x00000000 0x00000 0x00000 RW 0x4
Dasm.readelf38 LOAD 0x0000a0 0x080490a0 0x080490a0 0x0000e 0x0000e RW 0x1000
/third_party/flutter/skia/third_party/externals/icu/source/data/locales/
Dnus.txt70 "RW",
74 "RW",
/third_party/skia/third_party/externals/icu/source/data/locales/
Dnus.txt70 "RW",
74 "RW",
/third_party/icu/icu4c/source/data/locales/
Dnus.txt70 "RW",
74 "RW",

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