| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 56 RegPressure.resize(NumRC); in ResourcePriorityQueue()
58 std::fill(RegPressure.begin(), RegPressure.end(), 0); in ResourcePriorityQueue()
365 if ((RegPressure[RC->getID()] + in regPressureDelta()
367 (RegPressure[RC->getID()] + in regPressureDelta()
480 RegPressure[RC->getID()] += numberRCValSuccInSU(SU, RC->getID()); in scheduledNode()
491 if (RegPressure[RC->getID()] > in scheduledNode()
493 RegPressure[RC->getID()] -= numberRCValPredInSU(SU, RC->getID()); in scheduledNode()
494 else RegPressure[RC->getID()] = 0; in scheduledNode()
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| D | ScheduleDAGRRList.cpp | 1745 std::vector<unsigned> RegPressure; member in __anon1be34ab80311::RegReductionPQBase
1764 RegPressure.resize(NumRC); in RegReductionPQBase()
1766 std::fill(RegPressure.begin(), RegPressure.end(), 0); in RegReductionPQBase()
1789 std::fill(RegPressure.begin(), RegPressure.end(), 0); in releaseState()
2075 unsigned RP = RegPressure[Id]; in dumpRegPressure()
2101 if ((RegPressure[RCId] + Cost) >= RegLimit[RCId]) in HighRegPressure()
2120 if (RegPressure[RCId] >= RegLimit[RCId]) in MayReduceRegPressure()
2151 if (RegPressure[RCId] >= RegLimit[RCId]) in RegPressureDiff()
2166 if (RegPressure[RCId] >= RegLimit[RCId]) in RegPressureDiff()
2212 RegPressure[RCId] += Cost; in scheduledNode()
[all …]
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| D | SelectionDAGISel.cpp | 266 if (TLI->getSchedulingPreference() == Sched::RegPressure) in createDefaultScheduler()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | MachineLICM.cpp | 149 SmallVector<unsigned, 8> RegPressure; member in __anon1bc5e0380111::MachineLICMBase
190 RegPressure.clear(); in releaseMemory()
362 RegPressure.resize(NumRPS); in runOnMachineFunction()
363 std::fill(RegPressure.begin(), RegPressure.end(), 0); in runOnMachineFunction()
672 BackTrace.push_back(RegPressure); in EnterScope()
844 std::fill(RegPressure.begin(), RegPressure.end(), 0); in InitRegPressure()
867 if (static_cast<int>(RegPressure[Class]) < -RPIdAndCost.second) in UpdateRegPressure()
868 RegPressure[Class] = 0; in UpdateRegPressure()
870 RegPressure[Class] += RPIdAndCost.second; in UpdateRegPressure()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ResourcePriorityQueue.h | 52 std::vector<unsigned> RegPressure; variable
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| D | MachineScheduler.h | 403 IntervalPressure RegPressure; variable
427 RegClassInfo(C->RegClassInfo), RPTracker(RegPressure), in ScheduleDAGMILive()
447 const IntervalPressure &getRegPressure() const { return RegPressure; } in getRegPressure()
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| D | TargetLowering.h | 101 RegPressure, // Scheduling for lowest register pressure. enumerator
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 50 setSchedulingPreference(Sched::RegPressure); in WebAssemblyTargetLowering()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRISelLowering.cpp | 46 setSchedulingPreference(Sched::RegPressure); in AVRTargetLowering()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 1464 setSchedulingPreference(Sched::RegPressure); in ARMTargetLowering()
1766 return Sched::RegPressure; in getSchedulingPreference()
1777 return Sched::RegPressure; in getSchedulingPreference()
1785 return Sched::RegPressure; in getSchedulingPreference()
1790 return Sched::RegPressure; in getSchedulingPreference()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 367 setSchedulingPreference(Sched::RegPressure); in NVPTXTargetLowering()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 454 setSchedulingPreference(Sched::RegPressure); in AMDGPUTargetLowering()
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| D | SIISelLowering.cpp | 765 setSchedulingPreference(Sched::RegPressure); in SITargetLowering()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 122 setSchedulingPreference(Sched::RegPressure); in SystemZTargetLowering()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 132 setSchedulingPreference(Sched::RegPressure); in X86TargetLowering()
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