| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsRegisterBankInfo.cpp | 424 LLT RegTy = MRI.getType(Op.getReg()); in getInstrMapping() local
426 if (RegTy.isScalar() && in getInstrMapping()
427 (RegTy.getSizeInBits() != 32 && RegTy.getSizeInBits() != 64)) in getInstrMapping()
430 if (RegTy.isVector() && RegTy.getSizeInBits() != 128) in getInstrMapping()
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| D | MipsISelLowering.cpp | 4340 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8); in copyByValRegs() local
4341 const TargetRegisterClass *RC = getRegClassFor(RegTy); in copyByValRegs()
4349 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), in copyByValRegs()
4368 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); in passByValArg() local
4380 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, in passByValArg()
4407 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(), in passByValArg()
4419 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, in passByValArg()
4423 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); in passByValArg()
4459 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); in writeVarArgRegs() local
4460 const TargetRegisterClass *RC = getRegClassFor(RegTy); in writeVarArgRegs()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | RegBankSelect.cpp | 174 LLT RegTy = MRI->getType(MO.getReg()); in repairReg() local
177 if (RegTy.isVector()) { in repairReg()
178 if (ValMapping.NumBreakDowns == RegTy.getNumElements()) in repairReg()
183 RegTy.getSizeInBits()) && in repairReg()
184 (ValMapping.BreakDown[0].Length % RegTy.getScalarSizeInBits() == in repairReg()
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| D | LegalizerHelper.cpp | 130 bool LegalizerHelper::extractParts(Register Reg, LLT RegTy, in extractParts() argument
136 unsigned RegSize = RegTy.getSizeInBits(); in extractParts()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | MachineRegisterInfo.cpp | 95 const LLT RegTy = getType(Reg); in constrainRegAttrs() local
97 if (RegTy.isValid() && ConstrainingRegTy.isValid() && in constrainRegAttrs()
98 RegTy != ConstrainingRegTy) in constrainRegAttrs()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstructionSelector.cpp | 1531 const LLT RegTy = MRI.getType(DstReg); in selectDivRem() local
1532 assert(RegTy == MRI.getType(Op1Reg) && RegTy == MRI.getType(Op2Reg) && in selectDivRem()
1607 [RegTy](const DivRemEntry &El) { in selectDivRem()
1608 return El.SizeInBits == RegTy.getSizeInBits(); in selectDivRem()
1634 const TargetRegisterClass *RegRC = getRegClass(RegTy, *RegRB); in selectDivRem()
1660 if (RegTy.getSizeInBits() == 16) { in selectDivRem()
1664 } else if (RegTy.getSizeInBits() == 32) { in selectDivRem()
1668 } else if (RegTy.getSizeInBits() == 64) { in selectDivRem()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | LegalizerHelper.h | 148 bool extractParts(Register Reg, LLT RegTy, LLT MainTy,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 204 struct RegTy { struct
218 struct RegTy Reg;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 1494 template <VecListIndexType RegTy, unsigned NumRegs>
1509 assert((RegTy != VecListIdx_ZReg || NumRegs <= 4) && in addVectorListOperands()
1512 unsigned FirstReg = FirstRegs[(unsigned)RegTy][NumRegs]; in addVectorListOperands()
1514 FirstRegs[(unsigned)RegTy][0])); in addVectorListOperands()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 4836 class VDOT<bit op6, bit op4, RegisterClass RegTy, string Asm, string AsmTy,
4839 N3Vnp<0b11000, 0b10, 0b1101, op6, op4, (outs RegTy:$dst),
4840 (ins RegTy:$Vd, RegTy:$Vn, RegTy:$Vm), N3RegFrm, IIC_VDOTPROD,
4842 [(set (AccumTy RegTy:$dst),
4843 (OpNode (AccumTy RegTy:$Vd),
4844 (InputTy RegTy:$Vn),
4845 (InputTy RegTy:$Vm)))]> {
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 2865 MVT RegTy = MemTy == MVT::i64 ? MVT::i64 : MVT::i32; in SelectCMP_SWAP() local
2870 CurDAG->getVTList(RegTy, MVT::i32, MVT::Other), Ops); in SelectCMP_SWAP()
|