Home
last modified time | relevance | path

Searched refs:RegType (Results 1 – 25 of 25) sorted by relevance

/third_party/mesa3d/src/amd/compiler/
Daco_instruction_selection_setup.cpp241 get_reg_class(isel_context* ctx, RegType type, unsigned components, unsigned bitsize) in get_reg_class()
244 return RegClass(RegType::sgpr, ctx->program->lane_mask.size() * components); in get_reg_class()
464 RegType type = in init_context()
465 nir_dest_is_divergent(alu_instr->dest.dest) ? RegType::vgpr : RegType::sgpr; in init_context()
523 case nir_op_sdot_2x16_iadd_sat: type = RegType::vgpr; break; in init_context()
549 type = alu_instr->dest.dest.ssa.num_components == 2 ? RegType::vgpr : type; in init_context()
553 if (regclasses[alu_instr->src[i].src.ssa->index].type() == RegType::vgpr) in init_context()
554 type = RegType::vgpr; in init_context()
567 RegClass rc = get_reg_class(ctx, RegType::sgpr, num_components, bit_size); in init_context()
575 RegType type = RegType::sgpr; in init_context()
[all …]
Daco_validate.cpp303 check(instr->definitions[0].getTemp().type() == RegType::sgpr, in validate_ir()
306 check(instr->definitions[0].getTemp().type() == RegType::vgpr, in validate_ir()
317 check(i != 1 || (op.isTemp() && op.regClass().type() == RegType::sgpr) || in validate_ir()
320 check(i == 1 || (op.isTemp() && op.regClass().type() == RegType::vgpr && in validate_ir()
327 check(i != 0 || (op.isTemp() && op.regClass().type() == RegType::vgpr), in validate_ir()
329 check(i == 0 || (op.isTemp() && op.regClass().type() == RegType::sgpr) || in validate_ir()
337 check(i != 2 || (op.isTemp() && op.regClass().type() == RegType::vgpr && in validate_ir()
340 check(i == 2 || (op.isTemp() && op.regClass().type() == RegType::sgpr) || in validate_ir()
345 if (op.isTemp() && instr->operands[i].regClass().type() == RegType::sgpr) { in validate_ir()
364 check(instr->definitions[0].getTemp().type() == RegType::sgpr, in validate_ir()
[all …]
Daco_lower_to_cssa.cpp103 if (def.regClass().type() == RegType::sgpr && !op.isTemp()) { in collect_parallelcopies()
173 idom = b.regClass().type() == RegType::vgpr ? ctx.program->blocks[idom].logical_idom in dominates()
197 std::vector<uint32_t>& preds = var.type() == RegType::vgpr in intersects()
351 pred = copy.op.regClass().type() == RegType::vgpr ? ctx.program->blocks[pred].logical_idom in try_coalesce_copy()
387 emit_copies_block(Builder& bld, std::map<uint32_t, ltg_node>& ltg, RegType type) in emit_copies_block()
466 bool is_vgpr = cp.def.regClass().type() == RegType::vgpr; in emit_parallelcopies()
492 emit_copies_block(bld, ltg, RegType::vgpr); in emit_parallelcopies()
500 emit_copies_block(bld, ltg, RegType::sgpr); in emit_parallelcopies()
Daco_spill.cpp200 if (op.regClass().type() == RegType::vgpr && op.regClass().is_linear()) in next_uses_per_block()
410 if (op.regClass().type() == RegType::vgpr && op.regClass().is_linear()) in update_local_next_uses()
524 RegType type = RegType::vgpr; in init_live_in_vars()
527 if (type == RegType::vgpr && loop_demand.vgpr <= ctx.target_pressure.vgpr) in init_live_in_vars()
528 type = RegType::sgpr; in init_live_in_vars()
530 if (type == RegType::sgpr && loop_demand.sgpr <= ctx.target_pressure.sgpr) in init_live_in_vars()
539 (ctx.remat.count(pair.first) && type == RegType::sgpr)) && in init_live_in_vars()
548 if (type == RegType::sgpr) in init_live_in_vars()
550 type = RegType::sgpr; in init_live_in_vars()
576 type = reg_pressure.vgpr > ctx.target_pressure.vgpr ? RegType::vgpr : RegType::sgpr; in init_live_in_vars()
[all …]
Daco_instruction_selection.cpp270 if (val.type() == RegType::sgpr) { in as_vgpr()
272 return bld.copy(bld.def(RegType::vgpr, val.size()), val); in as_vgpr()
274 assert(val.type() == RegType::vgpr); in as_vgpr()
354 assert(dst_rc.type() == RegType::vgpr && it->second[idx].type() == RegType::sgpr); in emit_extract_vector()
381 if (vec_src.type() == RegType::sgpr) { in emit_split_vector()
387 rc = RegClass(RegType::vgpr, vec_src.bytes() / num_components).as_subdword(); in emit_split_vector()
415 if (dst.type() == RegType::sgpr) in expand_vector()
433 if (dst.type() == RegType::sgpr) in expand_vector()
536 RegClass rc = RegClass(RegType::vgpr, component_size).as_subdword(); in byte_align_vector()
543 if (dst.type() == RegType::vgpr) { in byte_align_vector()
[all …]
Daco_reduce_assign.cpp60 Temp reduceTmp(0, RegClass(RegType::vgpr, maxSize).as_linear()); in setup_reduce_temp()
61 Temp vtmp(0, RegClass(RegType::vgpr, maxSize).as_linear()); in setup_reduce_temp()
Daco_ir.h300 enum class RegType { enum
339 constexpr RegClass(RegType type, unsigned size) in RegClass()
340 : rc((RC)((type == RegType::vgpr ? 1 << 5 : 0) | size)) in RegClass()
346 constexpr RegType type() const { return rc <= RC::s16 ? RegType::sgpr : RegType::vgpr; } in type()
356 static constexpr RegClass get(RegType type, unsigned bytes) in get()
358 if (type == RegType::sgpr) { in get()
369 return get(RegType::vgpr, bytes).as_linear(); in resize()
415 constexpr RegType type() const noexcept { return regClass().type(); } in type()
797 constexpr bool isOfType(RegType type) const noexcept in isOfType()
1823 if (t.type() == RegType::sgpr)
[all …]
Daco_optimizer.cpp510 [](const Definition& def) { return def.regClass().type() == RegType::vgpr; }); in pseudo_propagate_temp()
513 if (temp.type() == RegType::vgpr && !vgpr) in pseudo_propagate_temp()
530 if (temp.type() == RegType::sgpr && !can_accept_sgpr) in pseudo_propagate_temp()
534 if (temp.type() == RegType::sgpr && !can_accept_sgpr) in pseudo_propagate_temp()
604 return op.isTemp() && op.getTemp().type() == RegType::vgpr; in is_operand_vgpr()
672 if (op.hasRegClass() && op.regClass().type() == RegType::sgpr) { in check_vop3_operands()
834 (tmp.type() == RegType::vgpr || ctx.program->chip_class >= GFX9)) { in can_apply_extract()
878 (tmp.type() == RegType::vgpr || ctx.program->chip_class >= GFX9)) { in apply_extract()
899 if (info.is_extract() && (info.instr->operands[0].getTemp().type() == RegType::vgpr || in check_sdwa_extract()
900 op.getTemp().type() == RegType::sgpr)) { in check_sdwa_extract()
[all …]
Daco_lower_to_hw_instr.cpp391 RegClass rc = RegClass(RegType::vgpr, size); in emit_dpp_op()
431 RegClass rc = RegClass(RegType::vgpr, size); in emit_op()
433 Operand src0(src0_reg, RegClass(src0_reg.reg() >= 256 ? RegType::vgpr : RegType::sgpr, size)); in emit_op()
814 if (reduction_needs_last_op && dst.regClass().type() == RegType::vgpr) { in emit_reduction()
827 if (dst.regClass().type() == RegType::sgpr) { in emit_reduction()
866 assert(input_data.regClass().type() == RegType::vgpr); in emit_gfx10_wave64_bpermute()
935 assert(input.regClass().type() == RegType::vgpr); in emit_gfx6_bpermute()
979 if (ctx->program->chip_class < GFX10 && src.def.regClass().type() == RegType::vgpr) in split_copy()
981 unsigned max_align = src.def.regClass().type() == RegType::vgpr ? 4 : 16; in split_copy()
1204 Definition(lo_reg, RegClass::get(RegType::vgpr, def.physReg().byte())); in do_copy()
[all …]
Daco_ir.cpp212 if (chip < GFX9 && !instr->operands[i].isOfType(RegType::vgpr)) in can_use_SDWA()
223 if (chip < GFX9 && !instr->operands[0].isOfType(RegType::vgpr)) in can_use_SDWA()
284 if (instr->definitions[0].getTemp().type() == RegType::sgpr && chip == GFX8) in convert_to_SDWA()
321 if (instr->operands.size() > 1 && !instr->operands[1].isOfType(RegType::vgpr)) in can_use_DPP()
551 if (def.getTemp().type() == RegType::vgpr) in needs_exec_mask()
680 (instr->operands[0].isTemp() && instr->operands[0].getTemp().type() == RegType::sgpr)) in can_swap_operands()
Daco_register_allocation.cpp169 if (rc.type() == RegType::vgpr) { in get_stride()
184 get_reg_bounds(Program* program, RegType type) in get_reg_bounds()
186 if (type == RegType::vgpr) { in get_reg_bounds()
397 PhysRegInterval regs = get_reg_bounds(ctx.program, vgprs ? RegType::vgpr : RegType::sgpr); in print_regs()
703 if (rc.type() == RegType::vgpr) { in adjust_max_used_regs()
850 (rc.type() == RegType::vgpr) ? (256 + ctx.max_used_vgpr) : ctx.max_used_sgpr; in get_reg_simple()
1318 if (rc.type() == RegType::sgpr && reg % get_stride(rc) != 0) in get_reg_specified()
1325 bool is_vcc = rc.type() == RegType::sgpr && vcc_win.contains(reg_win); in get_reg_specified()
1345 increase_register_file(ra_ctx& ctx, RegType type) in increase_register_file()
1347 if (type == RegType::vgpr && ctx.program->max_reg_demand.vgpr < ctx.vgpr_limit) { in increase_register_file()
[all …]
Daco_live_var_analysis.cpp203 assert(definition.getTemp().type() == RegType::sgpr); in process_live_temps_per_block()
249 if (insn->opcode == aco_opcode::p_phi && operand.getTemp().type() == RegType::sgpr) { in process_live_temps_per_block()
252 assert(operand.getTemp().type() == RegType::sgpr); in process_live_temps_per_block()
Daco_insert_NOPs.cpp412 if (def.regClass().type() != RegType::sgpr) { in handle_instruction_gfx6()
443 if (!op.isConstant() && !op.isUndefined() && op.regClass().type() == RegType::sgpr) in handle_instruction_gfx6()
504 if (def.regClass().type() == RegType::sgpr) { in handle_instruction_gfx6()
542 instr->operands[1].regClass().type() == RegType::vgpr && in handle_instruction_gfx6()
612 { return def.getTemp().type() == RegType::sgpr; }); in instr_writes_sgpr()
Daco_lower_phis.cpp325 assert(phi_src.regClass().type() == RegType::sgpr); in lower_subdword_phis()
326 Temp tmp = bld.tmp(RegClass(RegType::vgpr, phi_src.size())); in lower_subdword_phis()
Daco_optimizer_postRA.cpp91 assert(def.regClass().type() != RegType::sgpr || def.physReg().reg() <= 255); in save_reg_writes()
92 assert(def.regClass().type() != RegType::vgpr || def.physReg().reg() >= 256); in save_reg_writes()
Daco_print_ir.cpp94 } else if (rc.type() == RegType::sgpr) { in print_reg_class()
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
DIceAssemblerX8664.h886 template <typename RegType, typename RmType>
887 inline void emitXmmRegisterOperand(RegType reg, RmType rm);
933 template <typename RegType> GPRRegister gprEncoding(const RegType Reg) { in gprEncoding()
937 template <typename RegType>
938 bool is8BitRegisterRequiringRex(const Type Ty, const RegType Reg) { in is8BitRegisterRequiringRex()
940 std::is_same<typename std::decay<RegType>::type, ByteRegister>::value || in is8BitRegisterRequiringRex()
941 std::is_same<typename std::decay<RegType>::type, GPRRegister>::value; in is8BitRegisterRequiringRex()
962 template <typename RegType, typename RmType>
963 void assembleAndEmitRex(const Type TyReg, const RegType Reg, const Type TyRm,
985 template <typename RegType, typename RmType>
[all …]
DIceAssemblerX8632.h890 template <typename RegType, typename RmType>
891 inline void emitXmmRegisterOperand(RegType reg, RmType rm);
935 template <typename RegType> GPRRegister gprEncoding(const RegType Reg) { in gprEncoding()
958 template <typename RegType, typename RmType>
959 inline void AssemblerX8632::emitXmmRegisterOperand(RegType reg, RmType rm) { in emitXmmRegisterOperand()
DIceTargetLoweringMIPS32.cpp1629 Type RegType; in addProlog() local
1631 RegType = IceType_f32; in addProlog()
1633 RegType = IceType_i32; in addProlog()
1634 auto *PhysicalRegister = makeReg(RegType, Var->getRegNum()); in addProlog()
1635 StackOffset -= typeWidthInBytesOnStack(RegType); in addProlog()
1638 Func, RegType, SP, in addProlog()
1753 Type RegType; in addEpilog() local
1755 RegType = IceType_f32; in addEpilog()
1757 RegType = IceType_i32; in addEpilog()
1758 auto *PhysicalRegister = makeReg(RegType, (*RIter)->getRegNum()); in addEpilog()
[all …]
/third_party/mesa3d/src/amd/compiler/tests/
Dhelpers.cpp119 …RegClass cls(input_spec[i * 3] == 'v' ? RegType::vgpr : RegType::sgpr, input_spec[i * 3 + 1] - '0'… in setup_cs()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td5406 string kind2, RegisterOperand RegType,
5409 BaseSIMDThreeSameVectorTied<Q, U, 0b100, 0b10010, RegType, asm, kind1,
5410 [(set (AccumType RegType:$dst),
5411 (OpNode (AccumType RegType:$Rd),
5412 (InputType RegType:$Rn),
5413 (InputType RegType:$Rm)))]> {
5428 string kind2, RegisterOperand RegType,
5431 BaseSIMDThreeSameVectorTied<Q, U, size, 0b11101, RegType, asm, kind1,
5432 [(set (AccumType RegType:$dst),
5433 (OpNode (AccumType RegType:$Rd),
[all …]
DAArch64FrameLowering.cpp1910 enum RegType { GPR, FPR64, FPR128, PPR, ZPR } Type; enum
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DCodeGenPrepare.cpp6350 MVT RegType = TLI->getRegisterType(Context, TLI->getValueType(*DL, OldType)); in optimizeSwitchInst() local
6351 unsigned RegWidth = RegType.getSizeInBits(); in optimizeSwitchInst()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/
DTarget.td217 // RegType - Specify the list ValueType of the registers in this register
/third_party/mesa3d/docs/relnotes/
D21.2.0.rst1552 - aco: relax validation rules for p_reduce dst RegType