| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 4782 EVT ResVT = N->getValueType(0); in ReplaceLoadVector() local
4785 assert(ResVT.isVector() && "Vector load must have vector type"); in ReplaceLoadVector()
4790 assert(ResVT.isSimple() && "Can only handle simple types"); in ReplaceLoadVector()
4791 switch (ResVT.getSimpleVT().SimpleTy) { in ReplaceLoadVector()
4816 TD.getPrefTypeAlignment(ResVT.getTypeForEVT(*DAG.getContext())); in ReplaceLoadVector()
4826 EVT EltVT = ResVT.getVectorElementType(); in ReplaceLoadVector()
4827 unsigned NumElts = ResVT.getVectorNumElements(); in ReplaceLoadVector()
4897 Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res); in ReplaceLoadVector()
4904 SDValue BuildVec = DAG.getBuildVector(ResVT, DL, ScalarRes); in ReplaceLoadVector()
4927 EVT ResVT = N->getValueType(0); in ReplaceINTRINSIC_W_CHAIN() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 235 EVT ResVT = N->getValueType(0); in ScalarizeVecRes_OverflowOp() local
239 if (getTypeAction(ResVT) == TargetLowering::TypeScalarizeVector) { in ScalarizeVecRes_OverflowOp()
251 ResVT.getVectorElementType(), OvVT.getVectorElementType()); in ScalarizeVecRes_OverflowOp()
1367 EVT ResVT = N->getValueType(0); in SplitVecRes_OverflowOp() local
1370 std::tie(LoResVT, HiResVT) = DAG.GetSplitDestVTs(ResVT); in SplitVecRes_OverflowOp()
1374 if (getTypeAction(ResVT) == TargetLowering::TypeSplitVector) { in SplitVecRes_OverflowOp()
2056 EVT ResVT = N->getValueType(0); in SplitVecOp_VECREDUCE() local
2094 return DAG.getNode(N->getOpcode(), dl, ResVT, Partial, N->getFlags()); in SplitVecOp_VECREDUCE()
2099 EVT ResVT = N->getValueType(0); in SplitVecOp_UnaryOp() local
2105 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), in SplitVecOp_UnaryOp()
[all …]
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| D | SelectionDAG.cpp | 9333 EVT ResVT = N->getValueType(0); in UnrollVectorOverflowOp() local
9335 EVT ResEltVT = ResVT.getVectorElementType(); in UnrollVectorOverflowOp()
9340 unsigned NE = ResVT.getVectorNumElements(); in UnrollVectorOverflowOp()
9359 getBoolConstant(true, dl, OvEltVT, ResVT), in UnrollVectorOverflowOp()
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| D | LegalizeIntegerTypes.cpp | 229 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); in PromoteIntRes_Atomic0() local
231 N->getMemoryVT(), ResVT, in PromoteIntRes_Atomic0()
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| D | DAGCombiner.cpp | 6106 EVT ResVT = ExtractFrom.getValueType(); in extractShiftForRotate() local
6108 return DAG.getNode(Opcode, DL, ResVT, OppShiftLHS, NewShiftNode); in extractShiftForRotate()
14683 EVT ResVT = Use->getValueType(0); in canMergeExpensiveCrossRegisterBankCopy() local
14685 TLI.getRegClassFor(ResVT.getSimpleVT(), Use->isDivergent()); in canMergeExpensiveCrossRegisterBankCopy()
14689 if (ArgRC == ResRC || !TLI.isOperationLegal(ISD::LOAD, ResVT)) in canMergeExpensiveCrossRegisterBankCopy()
14703 ResVT.getTypeForEVT(*DAG->getContext())); in canMergeExpensiveCrossRegisterBankCopy()
14709 if (!TLI.isOperationLegal(ISD::LOAD, ResVT)) in canMergeExpensiveCrossRegisterBankCopy()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 3267 EVT ResVT = Op.getValueType(); in lowerBITCAST() local
3274 SDValue NewLoad = DAG.getLoad(ResVT, DL, LoadN->getChain(), in lowerBITCAST()
3281 if (InVT == MVT::i32 && ResVT == MVT::f32) { in lowerBITCAST()
3297 if (InVT == MVT::f32 && ResVT == MVT::i32) { in lowerBITCAST()
5445 SDValue SystemZTargetLowering::combineExtract(const SDLoc &DL, EVT ResVT, in combineExtract() argument
5473 return DAG.getUNDEF(ResVT); in combineExtract()
5503 EVT VT = MVT::getIntegerVT(ResVT.getSizeInBits()); in combineExtract()
5505 if (VT != ResVT) { in combineExtract()
5507 Op = DAG.getNode(ISD::BITCAST, DL, ResVT, Op); in combineExtract()
5543 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResVT, Op, in combineExtract()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 9616 bool AArch64TargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument
9618 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
9621 return (Index == 0 || Index == ResVT.getVectorNumElements()); in isExtractSubvectorCheap()
11158 EVT ResVT = N->getValueType(0); in performExtendCombine() local
11159 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT)) in performExtendCombine()
11166 if (!ResVT.isSimple() || !SrcVT.isSimple()) in performExtendCombine()
11184 unsigned NumElements = ResVT.getVectorNumElements(); in performExtendCombine()
11187 ResVT.getVectorElementType(), NumElements / 2); in performExtendCombine()
11200 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); in performExtendCombine()
12194 EVT ResVT = N->getValueType(0); in performVSelectCombine() local
[all …]
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| D | AArch64ISelLowering.h | 467 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
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| D | AArch64InstrInfo.td | 4830 multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT,
4833 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src128VT V128:$Rn),
4837 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src64VT V64:$Rn),
4850 multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,
4852 def : Pat<(ResVT (AArch64dup (i32 (trunc (extractelt (v2i64 V128:$Rn),
4856 def : Pat<(ResVT (AArch64dup (i32 (trunc (extractelt (v1i64 V64:$Rn),
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 522 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
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| D | ARMISelLowering.cpp | 16683 bool ARMTargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument
16685 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
16688 return (Index == 0 || Index == ResVT.getVectorNumElements()); in isExtractSubvectorCheap()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 5116 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument
5118 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
5123 if (ResVT.getVectorElementType() == MVT::i1) in isExtractSubvectorCheap()
5124 return Index == 0 || ((ResVT.getSizeInBits() == SrcVT.getSizeInBits()*2) && in isExtractSubvectorCheap()
5125 (Index == ResVT.getVectorNumElements())); in isExtractSubvectorCheap()
5127 return (Index % ResVT.getVectorNumElements()) == 0; in isExtractSubvectorCheap()
10222 MVT ResVT = Op.getSimpleValueType(); in LowerAVXCONCAT_VECTORS() local
10224 assert((ResVT.is256BitVector() || in LowerAVXCONCAT_VECTORS()
10225 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide"); in LowerAVXCONCAT_VECTORS()
10246 MVT HalfVT = ResVT.getHalfNumVectorElementsVT(); in LowerAVXCONCAT_VECTORS()
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| D | X86FastISel.cpp | 3582 EVT ResVT = VA.getValVT(); in fastLowerCall() local
3583 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; in fastLowerCall()
3584 unsigned MemSize = ResVT.getSizeInBits()/8; in fastLowerCall()
3589 Opc = ResVT == MVT::f32 ? X86::MOVSSrm_alt : X86::MOVSDrm_alt; in fastLowerCall()
|
| D | X86ISelLowering.h | 1157 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
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| D | X86ISelDAGToDAG.cpp | 4296 MVT ResVT = Setcc.getSimpleValueType(); in tryVPTESTM() local
4297 MVT MaskVT = ResVT; in tryVPTESTM()
4353 unsigned RegClass = getMaskRC(ResVT); in tryVPTESTM()
4356 dl, ResVT, SDValue(CNode, 0), RC); in tryVPTESTM()
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| D | X86InstrSSE.td | 6970 ValueType ResVT, ValueType OpVT, SchedWrite Sched> :
6973 [(set RC:$dst, (ResVT (X86VBroadcast (OpVT VR128:$src))))]>,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 7578 EVT ResVT = Op.getValueType(); in LowerSELECT_CC() local
7617 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
7620 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
7630 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
7639 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
7653 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
7656 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
7663 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
7669 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
7675 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
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| D | PPCISelDAGToDAG.cpp | 4141 EVT ResVT = VecVT.changeVectorElementTypeToInteger(); in trySETCC() local
4143 SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, ResVT, LHS, RHS), 0); in trySETCC()
4145 ResVT, VCmp, VCmp); in trySETCC()
4149 CurDAG->SelectNodeTo(N, VCmpInst, ResVT, LHS, RHS); in trySETCC()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetLowering.h | 2557 virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonPatterns.td | 305 class OpR_R_pat<InstHexagon MI, PatFrag Op, ValueType ResVT, PatFrag RegPred>
306 : Pat<(ResVT (Op RegPred:$Rs)), (MI RegPred:$Rs)>;
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